Electronic – Difference between buffer and mailbox

buffercanfifomicrocontrolleruart

Peripherals in Micro-controllers usually provide a way for us to send and receive data from it. Usually this are memory mapped registers.

I have come across few terminologies. The most often used one is a buffer and probably a FIFO. But when working with CAN controllers, I came across Mailboxes.

Now I am confused.

What is the difference between a buffer and a mailbox. Or a FIFO and a mailbox.

Thanks!

Best Answer

A buffer is simply a collection of data registers that your program can access. In case of CAN, there is usually one or several "control field registers" where you can find the CAN identifier, message data length, RTR and such things. Followed by 8 bytes of the actual data.

A FIFO (first in first out) is simply a number of buffers, that form a queue. The first item to arrive in the queue is the first to leave. This is handled by hardware, so that you don't have to trigger an interrupt to service each and every CAN message. Most commonly there will be a Rx FIFO for received messages - this makes most sense since these would be causing interrupts, but some CAN controllers also support some manner of Tx FIFO.

In the case of Tx FIFO, it is usually just a mechanism to allow you have several out-going messages (usually 3), but have the CAN controller pick the one with lowest CAN identifier at the next point of message arbitration on the bus. There are also plenty of dumb CAN controllers which requires you to set a manual "Tx prio" instead of simply using the CAN identifier. Avoid these.

It is possible that some microcontrollers support DMA for CAN buffers, so that you can have them stored directly in some convenient chunk of RAM, instead of having to repeatedly poll/interrupt trigger on the CAN peripheral's registers.

Mailboxes is a different alternative. Each mailbox is a buffer (rx and/or tx), but it can be configured to only work with one specific CAN identifier. Meaning that it also have a receive flag and maybe also interrupt possibilities. These are perfect for systems where your MCU is only interested in a limited amounts of identifiers.

One more advanced, but fairly common setup, is to combine a Rx FIFO with mailboxes, so that high priority messages will end up in their dedicated mailbox, while everything else ends up in the FIFO. This could be a good solution for more advanced CAN applications like for example CANopen, where you have countless possible identifiers on the same bus.

Related Solutions

How to get data from one micro controller to another using UART

I dont understand your confusion. You want to communicate between the two controllers with UART, then ofcourse both of them need UART capabilities and code for this. Your computer has drivers and software for dealing with this, so your microcontroller also needs a driver for it.

Your ATmega32 need UART TX functionality, while AT90USB1287 need UART RX functionality. Having already written both TX and RX for your ATmega32, writing the UART RX routine for AT90 should be a breese. You could add a bitvalue of some kind, identifying that the UART RX on AT90 is coming from your ATmega32, and directly pass it through to USB.

EDIT: Code from AVRFreaks that is written for at90usb1287

#include <avr/io.h> 
#include <util/delay.h> 

#define RXC      (RXC1) 
#define TXC      (RXC1) 
#define UCSRC    (UCSR1C) 
#define UCSRB    (UCSR1B) 
#define UCSRA    (UCSR1A) 
#define UDR      (UDR1) 
#define UBRRL    (UBRR1L) 
#define UBRRH    (UBRR1H) 
#define UBRR     (UBRR1) 
#define UDRE     (UDRE1) 
#define RXCIE    (RXCIE1) 
#define TXEN     (TXEN1) 
#define RXEN     (RXEN1) 
#define UCSZ0    (UCSZ10) 
#define UCSZ1    (UCSZ11) 
#define UMSEL0   (UMSEL10) 
#define UMSEL1   (UMSEL11) 

#define FRAMING_ERROR (1<<FE1) 
#define PARITY_ERROR (1<<UPE1) 
#define DATA_OVERRUN (1<<DOR1) 
#define DATA_REGISTER_EMPTY (1<<UDRE1) 
#define RX_COMPLETE (1<<RXC1) 

#define FOSC 16000000 

typedef unsigned char       Uchar; 
typedef unsigned long int   Uint32; 

#define Wait_USART_Ready() while (!(UCSR1A & (1<<UDRE1))) 

#define lowByte(w) ((uint8_t) ((w) & 0xff)) 
#define highByte(w) ((uint8_t) ((w) >> 8)) 

int main(void) 
{ 
/* Disable clock division */ 
clock_prescale_set(clock_div_1); 
   UBRRH = (Uchar)((((Uint32)FOSC)/((Uint32)USART_BAUDRATE*16)-1)>>8); 
   UBRRL = (Uchar)(((Uint32)FOSC)/((Uint32)USART_BAUDRATE*16)-1) & 0x0ff; 

   UCSRB |= (1 << RXEN) | (1 << TXEN); 
   UCSRC |= (1 << UCSZ1) | (1 << UCSZ0); 

   char ReceivedByte; 
   for (;;) // Loop forever 
   { 
      while ((UCSRA & (1 << RXC)) == 0) {}; // Do nothing until data have been received and is ready to be read from UDR 
      ReceivedByte = UDR; // Fetch the received byte value into the variable "ByteReceived" 

      while ((UCSRA & (1 << UDRE)) == 0) {}; // Do nothing until UDR is ready for more data to be written to it 
      UDR = ReceivedByte; // Echo back the received byte back to the computer 
   } 
}

Electronic – A simple FIFO buffer in verilog

Your read pointer and write pointer both need to travel in the same direction. Generally they are incremented, but decrementing also works, so long as you do the same for both. One method for full/empty detection is to use M+1 bit registers for the read and write pointer. If all M+1 bits match, then the FIFO is empty. However, if all bits match except the MSB, then the FIFO is full. Presuming you use a true dual port memory for storage (i.e. an FPGA block RAM), no locking is necessary as dual port RAM supports simultaneous reading and writing. No need for any isEmpty and isFull registers or a lastOp register if you can glean all of that information from the read and write pointers with simple combinatorial logic. However, you will need logic to prevent the write pointer from being changed when the FIFO is full or the read pointer from being changed when the FIFO is empty.

Best Answer

Related Solutions

How to get data from one micro controller to another using UART

Electronic – A simple FIFO buffer in verilog

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