Electronic – differential pair impedance and length matching

From the text, this appears to be a USB high speed interface.

The signal pair will have very little current, but you need to keep losses to a minimum.

The losses in high speed tracks are dominated by:

Skin Effect. This is because as signal transition rates become faster, the self-inductance of the conductor forms a high impedance in the centre of the conductor. A wider track reduces this loss (but it has diminishing returns above about 8 thou).

Dielectric absorption also causes losses. There is an excellent description of them here.

Another cause of losses is differential to common mode conversion, usually caused by a length mismatch between the pair.

The practical implementation of a controlled impedance pair depends whether you have a plane layer which is immediately below the signals; I will assume for now that you do and it is spaced 5 thou away from the signals (implies a 4 layer or higher PCB). The actual distance is determined by the various requirements of the PCB; a 5 thou core is commonly used (although many thicknesses exist).

I usually use 6 thou tracks for USB high speed (a decent trade-off for skin effect and PCB real estate); the gap between the pair can now be calculated by any number of tools.

For the geometry above, my calculations yield a trace separation of 4 thou using 1 ounce copper (commonly the finished thickness on outer layers).

If you do not have a plane layer, there are other techniques such as differential coplanar waveguide; just what technique I use is determined by the PCB geometries.

There is no one size fits all, but using a 5 thou to 6 thou track width as a starting point helps narrow things down.

With clarifications added, here is my answer. The particular device of interest is a 16-bit DAC. It has a PARALLEL interface, and settling time is 5us. This means that the converter should not be used with data changes faster than 5us (200 kHz sampling). This means that all concerns about edge rate and impedance matching have little to no grounds. The parallel interface with separate strobe and data has enough room at 5us rate to avoid any ringing that might emerge due to trace impedance mismatches. That's why the TI evaluation board does not have any special precautions for data input connector, and uses the cheapest 0.100" IDC headers. The 0.100 connectors have typical impedance of 100-120 Ohms, and the 10mil trace over 14mil substrate comes up to 78 Ohms.

Now, to get nice edges out of this setup, it is advisable to have the same kind of traces on the baseboard, and, since the drivers are thought of fast LVC245 nanosecond-grade buffers, a set of in-series resistors of about 47 Ohms would be in order, on driver side. They can be later adjusted for the best waveform. But again, you can do nothing, and the DAC interface will work just fine.