adcdifferentialserpentine-trace
I am routing a 16 bit ADC chip, the LTC2217 (datasheet) to FPGA. Each bit is an LVDS pair and I know +/- of the pair should be the same length but what about from pair to pair? I have 2 of these chips, 18 pairs, if you include OF and CLK, 36 pairs of LvDS having to be meandered to the same length becomes somewhat messy.
IE say bit 1 is 35mm and bit 0 is 37mm, how far off, if any are they allowed to be? I assume it has to do with sampling frequency, which for this chip is 105Msps.
While the length and impedance are both important, 1mm of length differential will not affect your system's performance in any way, even for usb-2.0 high-speed.
From the USB spec:
7.1.3 Cable Skew
The maximum skew introduced by the cable between the differential signaling pair (i.e., D+ and D- (TSKEW)) must be less than 100 ps and is measured as described in Section 6.7.
Assuming a perfect propagation velocity (i.e. C, the speed of light), a differential length of ~2.99 cm would produce a skew of 100 ps. As such, your 1 mm of trace length differential will not be a problem.
Added: On a real PCB, your signals travel slower than speed of light. For a stripline (inner layer) you divide the speed of light in vacuum by the square root of the relative dielectric constant (e_r). So about half speed. This means the 100ps is more like 15mm. For the outer layers, the speed is slightly higher (about 10%).
I'm not sure where you have read that the squiggle design is used for this purpose, i.e. path length matching. From what I can find the only place where a squiggle (like the one you've drawn) is intentionally used in RFID squiggle antennas; and you probably don't want to build one of those on your board!
Below is an example of path length matching from a book I've read (Jacob et al. Memory Systems). There are one or two squiggly looking paths there but only with one or two periods at the most. The pattern shown there seems to prefer a high amplitude of the "squiggle" so that it has a low number of periods/repetitions. Most other routes shown there are lengthened in some way but not by squiggles. The most common lengthening method used there seems to be making pentagonal U-turns (a term I just made up because I don't know an established one) so that an exterior polyline is naturally longer than an interior one. I don't know what software is used to generate those designs (but it's a good question).
After more searching, it seems that a trade term for the squiggles when applied to trace length matching is "serpentine traces".
And I found an article discussing those: A New Slant on Matched-Length Routing by Barry Olney... Well, the article is actually about proposing an alternative to serpentines, but it does have some background before it gets to comparison. It does seem to me however that the very long serpentines shown in that article are for demonstrative/contrast purposes. I've seen at least two dozen network card models up closely in my computing life (in 20+ years) and I cannot remember noticing a pronounced squiggle like yours (or the one in that article) on any of their PCBs... Now it may have existed in the inner layers (on the few boards that had more than two) where it was not visible. Some cards do route their differential signals on the inner layers, as microstrip.
With this serpentine terminology, it turned out they are standard textbook subject. Thierauf's Understanding Signal Integrity book has a couple of pages on this. Alternative terms are (according to that textbook): "meander or trombone traces". If I get this right, the number of periods is to be minimized because each contributes to a ladder-like waveform created by crosstalk between the U-turns, as excerpted below from the aforementioned textbook. This is alas a purely theoretical analysis. 
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The book also says that this is only an approximative solution and that a "3D field solver" is needed to fully simulate the real behavior; for example, the signal actually propagates faster in a serpentine than the 2D trace length would indicate. I intuited correctly the recommendation the book was going to draw from that graph; quoting it below:
Because the maximum coupled voltage grows with the number of segments in the serpentine, when laying out a serpentine, it is best to use a fewer number of long segments instead of a greater number of short ones. Fewer segments also mean fewer corners and less uncertainty in the timing and impedance. For these reasons the segments should be long (typically greater than the signal rise time) and few in number. Also, because crosstalk increases as the traces are tightly packed together, laddering can be reduced by increasing the separation between segments.
Finally, the book also mentions placing a grounded guard trace between segments in a serpentine to (further) reduce laddering caused by crosstalk. The book also lists/cites a few more in-depth papers on this serpentine issue:
On a more practical note, NXP has an app note DisplayPort PCB layout guidelines (AN10798) that touches on several aspects of trace lenght mathcing on pp. 4-6. They recommend the serpentine design shown below, which also obeys other rules, like not allowing too much distance between differential pairs.
Best Answer
The answer is driven by the output timing diagram of your ADC, shown here:
The chip provides a clock signal synchronized to the data. The clock falling edge is in the middle of the data valid interval as they leave the chip.
At maximum data rate, the clock period is about 10 ns.
This means you need to keep all your data signals aligned to the clock, with skew no more than 3 or 4 ns.
Since propagation velocity on the board is somewhere in the neighborhood of 40 cm / ns, this should be relatively easily achieved. To be tidy, I'd shoot for no more than 1 or 2 cm of trace length difference between any data signal and the clock.