Electronic – Dividing multi-bit port into inputs for 2 gates

I have written a little testbench that demonstrates the problem stand-alone:

module testbench;

integer i, j = 0;
reg [31:0] randval;

initial begin
    for (i = 0; i < 100000; i = i+1) begin
        randval = $random;
        if (randval[0 +: 6] == 0) begin
            $display("%8d %6d: %x -> %d %d", i, j, randval, randval[0 +: 6], randval[24 +: 4]);
            if (randval[24 +: 4] != 0) $finish;
            j = j + 1;
        end
    end
    $display("IEEE Std 1364-2005 $random (rtl_dist_uniform(seed, LONG_MIN, LONG_MAX)) sucks!");
end

endmodule

The really interesting thing here is that the exact behavior of $random is defined in IEEE Std 1364-2005. There is actually C code in the standard (pages 317 and 318). I don't want to quote it here in full, but a copy of the code can be found for example in Icarus Verilog:

https://github.com/steveicarus/iverilog/blob/master/vpi/sys_random.c

Calling $random in Verilog equals to calling rtl_dist_uniform(&a_seed, INT_MIN, INT_MAX) in this C file.

So what you demonstrated here is not only a weakness in $random of just one particular simulator, but a weakness in $random in general.

One solution would be to simply implement your own random number generator. I often use the Xorshift family of random number generators because they work fairly well and are easy to implement:

http://en.wikipedia.org/wiki/Xorshift

The following example uses a 64 bit xorshift to generate 32 bit numbers:

module testbench;

reg [63:0] xorshift64_state = 64'd88172645463325252;

task xorshift64_next;
    begin
        // see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
        xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
        xorshift64_state = xorshift64_state ^ (xorshift64_state >>  7);
        xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
    end
endtask

integer i;
initial begin
    for (i = 0; i < 100; i = i+1) begin
        xorshift64_next;
        $display("%x", xorshift64_state[31:0]);
    end
end

endmodule

Verilog strengths can be a bit of complicated process understand. To get the full breath of understanding read: IEEE Std 1800-2012 § 10.3, 21.2.1.5, and 28.10 through 28.16.

To print the strength of a bit in a display message, use %v instead of %b. (§ 21.2.1.5)

Verilog mostly works in the digital logic space. Verilog strength only comes into play when two or more assignments continuously drive the same net as a from of conflict resolution. The strength value does not propagate through assignment statements. The strength value can be passed through the verilog switch primitives: nmos, pmos, tranif1, tranif0, cmos, tran, plus resistive switch primitives (which weakens the strengths on pass-through). For verilog primitives switches refer to IEEE Std 1800-2012 § 28.7 through 28.9.

assign (pull1,pull0)  bus = pullup_en ? 1'b1 : 1'bz;
assign                bus = output_en ? value : 1'bz;

assign                out = bus;
assign (weak1,weak0) outw = bus;
cmos inst_name (outs, bus, 1'b1, 1'b0);

// pullup_en output_en  |  out(%v)         outw(%v)        outs(%v)
// ---------------------+----------------------------------------------
//       0         0    |  1'bx(StX)       1'bx(WeX)       1'bz(HiZ)
//       0         1    |  value(St1,St0)  value(We1/We0)  value(St1/St0)
//       1         0    |  1'b1(St1)       1'b1(We1)       1'b1(Pu1)
//       1         1    |  value(St1,St0)  value(We1/We0)  value(St1/St0)

Pullup/pulldown logic from a standard cells libraries provide by your vendor can be used for synthesis. Some synthesizers have pragmas to indicate a pullup/pulldown on a bus. Out side of that, verilog strength is typically not synthesizable. FPGAs have limited bidirectional bus support; if any. ASICs typically try to minimize the size and use of a bidirectional buses.