Verilog – Missing Connection for Port Issue

modelsimmodulesimulationverilog

I was creating a circuit using two dual input AND gates into a dual input NOR using three modules and module instantiation.

The first module is for the AND inputs and the second module is for the NOR. Both of these modules work correctly and this was verified using waveform simulation and checking the truth tables.

When I try to simulate the third module aoi22.v I get an error on this line
" orInv2 _orInv2_2 ( ._and1(_and1), ._and2(_and2),.f(f) ); " Missing conneciton for port _and1, _and2. When I take out the .f(f) I get an error Missing connection for port f? Any suggestions on how to fix this?

module and22 (input i1,i2,i3,i4, output _and1,_and2); 
    assign _and1 = i1 & i2;
    assign _and2 = i3 & i4;
endmodule

module orInv2 (input _and1, _and2, output f); 
    assign f = !(_and1 | _and2);
endmodule

module aoi22 ( input i1, i2, i3, i4, output _and1, _and2, f);

    and22 _and22_1 ( .i1(i1), .i2(i2), .i3(i3), .i4(i4) );
    orInv2 _orInv2_2 ( ._and1(_and1), ._and2(_and2),.f(f) ); 

endmodule

Best Answer

module and22 (input i1,i2,i3,i4, output _and1,_and2); 
    assign _and1 = i1 & i2;
    assign _and2 = i3 & i4;
endmodule

module orInv2 (input _and1, _and2, output f); 
    assign f = !(_and1 | _and2);
endmodule

module aoi22 ( input i1, i2, i3, i4, output f);
    logic o_and1;
    logic o_and2;

    and22 _and22_1 ( .i1(i1), .i2(i2), .i3(i3), .i4(i4), ._and1(o_and1), ._and1(o_and2) );
    orInv2 _orInv2_2 ( ._and1(o_and1), ._and2(o_and2),.f(f) ); 
endmodule

Related Solutions

Verilog: Pass a vector as a port to a module

The code you showed has a few problems:

You don't show how error_count is declared in the top-level module. If error_count is just declared as wire error_count;, you only have a single bit of your counter connected between the counter module and the lcd module.
You don't show how the counter is updated in the counter module. You could have a bug there that results in the counter never updating. Since it is initialized to 0, you'd always have a 0 output from the counter module.
You don't show any clock input to the counter module. If clock is not connected, error_counter will never be updated.
You say that lcd has a clock input, but you don't show that it actually does, and you don't show any code where it matters.
You don't show how your clock is generated. If there's no clock, the counter won't updated.
You don't show the complete input and output ports to either module. With your coding style it's easy to connect a wrong input to a wrong port. I much prefer to intantiate modules with the syntax like

counter counter1 ( .clk( clock ) , .error_count( error_count ) );

With this style, the order of naming the in's and out's in the instantiation doesn't matter.
You haven't shown any reset signal, but you probably have one. If the reset is stuck in the active state, probably the error_count won't ever increment.

Electronic – Verilog – Referencing Flattened Busses in Module Instantiation

It seems like you are running into Verilog's Escape identifiers gotcha:

§2.7.1 Escaped identifiers

Escaped identifiers shall start with the backslash character () and end with white space (space, tab, newline). They provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).

Neither the leading backslash character nor the terminating white space is considered to be part of the identifier. Therefore, an escaped identifier \cpu3 is treated the same as a nonescaped identifier cpu3.

So not only you need to properly write down escaped port name, but you also need to make sure you don't forget to put a whitespace at the end. For example:

DES_SBOX1 feistel( .CLK(CLK_tb),
                 .\ptext[5] (ptext_tb[5]),
                 .\ptext[4] (ptext_tb[4]),
  ...

Hope it helps. Good Luck!

Best Answer

Related Solutions

Verilog: Pass a vector as a port to a module

Electronic – Verilog – Referencing Flattened Busses in Module Instantiation

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