Electronic – Verilog – Referencing Flattened Busses in Module Instantiation

verilog

I have a verilog gate-level netlist generated by Synopsys Design Compiler.

DC was directed to flatten all busses and ports when creating the netlist, and the module declaration is given below:

module DES_SBOX1 ( CLK, \ptext[5] , \ptext[4] , \ptext[3] , \ptext[2] , 
    \ptext[1] , \ptext[0] , \key[5] , \key[4] , \key[3] , \key[2] , 
    \key[1] , \key[0] , \ctext[3] , \ctext[2] , \ctext[1] , 
    \ctext[0]  );

My problem is that when I go to use this module in a testbench, I receive syntax errors because I am not sure how to reference the ports names (because of the back-slash.)

Here is an attempt at instantiating one of these modules:

DES_SBOX1 feistel( .CLK(CLK_tb),
                 .ptext[5](ptext_tb[5]),
                 .ptext[4](ptext_tb[4]),
                 .ptext[3](ptext_tb[3]),
                 .ptext[2](ptext_tb[2]),
                 .ptext[1](ptext_tb[1]),
                 .ptext[0](ptext_tb[0]),
                 .key[5](1'b0),
                 .key[4](1'b0),
                 .key[3](1'b0),
                 .key[2](1'b0),
                 .key[1](1'b0),
                 .key[0](1'b0),
                 .ctext[5](ctext_tb[5]),
                 .ctext[4](ctext_tb[4]),
                 .ctext[3](ctext_tb[3]),
                 .ctext[2](ctext_tb[2]),
                 .ctext[1](ctext_tb[1]),
                 .ctext[0](ctext_tb[0]),
                );

…and here is the error message from Modelsim PE:

** Error: C:\Users\Kristin\Desktop\des_feistel_90nm\testbench.v(14): (vlog-2730) Undefined variable: 'ptext'.

** Error: C:\Users\Kristin\Desktop\des_feistel_90nm\testbench.v(14): near "[": syntax error, unexpected '[', expecting ')'

I've also tried using the back-slash in the instantiation itself, like so:

 .\ptext[5](ptext_tb[5])

..but this also gives a syntax error.

I'm wondering what the significance of the back-slash is in the first place?

Any ideas of how to correctly instantiate this module are greatly appreciated.

Thanks in advance!

-k

Best Answer

It seems like you are running into Verilog's Escape identifiers gotcha:

ยง2.7.1 Escaped identifiers

Escaped identifiers shall start with the backslash character () and end with white space (space, tab, newline). They provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).

Neither the leading backslash character nor the terminating white space is considered to be part of the identifier. Therefore, an escaped identifier \cpu3 is treated the same as a nonescaped identifier cpu3.

So not only you need to properly write down escaped port name, but you also need to make sure you don't forget to put a whitespace at the end. For example:

DES_SBOX1 feistel( .CLK(CLK_tb),
                 .\ptext[5] (ptext_tb[5]),
                 .\ptext[4] (ptext_tb[4]),
  ...

Hope it helps. Good Luck!

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