I am trying to make a module that will work like a queue with 4 slots. It is for an elevator and the currSt is the current state and destination is the first item in queue. 4'b1111 is like NULL. The problem here is that the queue doesn't get the input from the keyboard to be stored in the 4 free places. `
module Queue(
input clk, slowclk,
input[3:0] cs,
output[3:0] currstat, des,
input[3:0]keycode,
output reg go
);
reg currSt;
initial currSt = 4'b1;
//1111 = empty place in queue
reg queueItem1 = 4'b1111;
reg queueItem2 = 4'b1111;
reg queueItem3 = 4'b1111;
reg queueItem4 = 4'b1111;
//continuous assignment
assign currstat = currSt;
assign des = (queueItem1 == 4'b1111)?currSt:queueItem1;
always@(posedge clk) begin
if ((keycode == 4'b0001)
||(keycode == 4'b0010)
||(keycode == 4'b0100)
||(keycode == 4'b1000))
begin
if(queueItem1 == 4'b1111)
queueItem1 = keycode;
else if(queueItem2 == 4'b1111)
queueItem2 = keycode;
else if(queueItem3 == 4'b1111)
queueItem3 = keycode;
else if(queueItem4 == 4'b1111)
queueItem4 = keycode;
//else do nothing
end
//adds new key pressed to queue
if (keycode == 4'b0001
|| keycode == 4'b0010
|| keycode == 4'b0100
|| keycode == 4'b1000)
begin
if (queueItem1 != keycode
&& queueItem2 != keycode
&& queueItem3 != keycode
&& queueItem4 != keycode)
begin
if (queueItem1 == 4'b1111
&& queueItem2 == 4'b1111
&& queueItem3 == 4'b1111
&& queueItem4 == 4'b1111)
queueItem1 = keycode;
else if (queueItem1 != 4'b1111
&& queueItem2 == 4'b1111
&& queueItem3 == 4'b1111
&& queueItem4 == 4'b1111)
queueItem2 = keycode;
else if (queueItem1 != 4'b1111
&& queueItem2 != 4'b1111
&& queueItem3 == 4'b1111
&& queueItem4 == 4'b1111)
queueItem3 = keycode;
else if (queueItem1 != 4'b1111
&& queueItem2 != 4'b1111
&& queueItem3 != 4'b1111
&& queueItem4 == 4'b1111)
queueItem4 = keycode;
//else don't add the new one in the queue
end
//else if any of the slots is equal the keycode then dont add it
end
//check if current state matches with the request queue
if (currSt == 4'b1000
|| currSt == 4'b0100
|| currSt == 4'b0010
|| currSt == 4'b0001)
begin
if (queueItem1 == currSt) begin
queueItem1 = queueItem2;
queueItem2 = queueItem3;
queueItem3 = queueItem4;
queueItem4 = 4'b1111;
go = 0;
end else if (queueItem2 == currSt) begin
queueItem2 = queueItem3;
queueItem3 = queueItem4;
queueItem4 = 4'b1111;
go = 0;
end else if (queueItem3 == currSt) begin
queueItem3 = queueItem4;
queueItem4 = 4'b1111;
go = 0;
end else if (queueItem4 == currSt) begin
queueItem4 = 4'b1111;
go = 0;
end
//if current state is not in the request queue
else
go = 1;
end
end
always@(posedge slowclk)//change current state to new state
currSt <= cs;
endmodule
Best Answer
The thing is that the register was supposed to be a 4 bit one and I declared it as 1 bit. There were too many warnings and my brain couldn't process them yesterday but I found it out today while trying to debug this crap. I suggest you all check the number of bits and the warnings carefully.
~over and closed~