Verilog: including one module in another module

verilog

I am beginner in Verilog. So I am confused in coding in Verilog. Can I use one module in another module?

module pn(
  input p,
  input n,
  input clk,
  output reg q
);

  initial begin
    q = 0;
  end

  always @(posedge clk) q=(q&n)|((~q)&p);

endmodule

I want to use it in following module

module ic2323(
  input p0, 
  input n0, 
  input p1, 
  input n1, 
  input clk, 
  output q0, 
  output q1, 
  output x
);

endmodule

Is it possible?

EDIT:

 x=q0~^q1;

this code gives error

Reference to scalar wire 'x' is not a legal reg or variable lvalue

Illegal left hand side of blocking assignment

Best Answer

Sure, if you couldn't build up a hierarchy, HDLs would be rather limited.

For example, you could have:

module ic2323(
  input p0, 
  input n0, 
  input p1, 
  input n1, 
  input clk, 
  output q0, 
  output q1, 
  output x
);

  // Instantiate a pn for p0, n0 and q0.
  pn pn_a(
    .p   (p0),
    .n   (n0),
    .clk (clk),
    .q   (q0)
  );

  // Instantiate another pn for p1, n1 and q1
  pn pn_b (
    .p   (p1),
    .n   (n1),
    .clk (clk),
    .q   (q1)
  );

  // XNOR the two outputs together
  assign x = ~(q0 ^ q1);

endmodule
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