Electronic – Execute module one after another using flag status

verilog

I want to execute 2 modules, one after another using one flag signal

What changes do I have to do in code below to the modules. I have used delay_4 and multiply.

module iir_model(yout,temp1,win,clk);
  input  [3:0] win;
  output [3:0] yout;
  wire   [3:0] yout;
  input        clk;
  output [3:0] temp1;
  wire   [3:0] temp1;

  delay_4      a1(temp1,win,clk);
  multiply_4  (yout,win,temp1);
endmodule

delay_4:

module delay_4(data_out,data_in,clk);
  input [3:0] data_in;
  input clk;
  output [3:0] data_out;

  reg [3:0] data_out;
  reg [2:0] counter=4'b000;
  reg [3:0] temp;
  reg carry;

  integer i=0;

  always @(posedge clk)
  begin 
    i=i+1;
    if(i==1)
      temp=data_in;
    if(i>1)
    begin
      if(counter!=4'b100)
      begin
        carry=temp[0];
        temp=temp>>1'b1;
        temp[3]=carry;
        $monitor ($time," clk=%b,  counter=%b ,temp=%b ,carry=%b,data_out=%b",clk, counter,temp,carry,data_out);
        counter=counter+1;
      end
      data_out=(temp==data_in)?temp:4'b0000;
    end
  end
endmodule

multiply_4:

module multiply_4(z,x,y);
  input  [3:0] x,y;
  output [7:0] z;
  reg    [7:0] t;
  reg    [7:0] z;

  integer i,j;
  always @ (x or y)
  begin
    z = 8'b0;
    for(i = 0; i < 4 ; i = i + 1)
    begin
      t = 8'b0;
      if(y[i])
      begin
        t[i]   = x[0];
        t[i+1] = x[1]; 
        t[i+2] = x[2];
        t[i+3] = x[3];
      end
      z = z + t;
    end
  end 
endmodule

Best Answer

In Verilog, things don't execute one after the other, they execute in parallel. If you want to feed the results of one module into the inputs of another (ie a pipeline) then you just create the wires and connect them to the appropriate inputs and outputs.

I'm not even a reasonable Verilogger, so I can't see immediately what your problem is, but it might help to use named associated rather than positional association to do the wiring as its easier to see mistakes in port ordering that way.

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