Electronic – Does it matter if differential pairs have no reference plane or cross reference planes

I'll try to answer this briefly, but a great resource for this type of question is Eric Bogatin's Signal and Power Integrity -- Simpified.

You've listed and described several very high speed protocols that have signal edge rates in the hundreds of picosecond range. What this means is that even traces of just a couple of inches can be considered as electrically long, and that these transmission channels must be routed as transmission lines.

Put very, very briefly, presenting a transmission line with a known impedance to a high speed driver (serial transceiver on the input/output of a SerDes) allows the transmission of data cross that line without deletrious signal reflections that can interfere with successful communication. This can manifest as intersymbol interference (ISI), crosstalk, additional jitter rendering an UI (unit interval) unusable and many other effects. Recall that some of these protocols (like PCIe) are pushing in excess of 8GT/s over conventional copper on low-cost FR-4; in order to do this, designers must take care to do all they can to provide a high-quality channel for data transmission.

A given protocol (or specification) generally lists a desired characteristic impedance. As an example, Intel may request PCI Express traces for their Xeon platforms be routed as "100 ohm differential pairs". This means that they have qualified and designed their PCI Express transceivers to expect a 100 ohm characteristic impedance transmission line for data transfer. USB commonly requires 90 ohms, RS-422 can be 120 ohms, and Ethernet is 100 ohm. I'm not going to go into single-ended transmission line structures in this post, but as mentioned below in the comments, to an approximate first order, you could consider each 'half' of the structures below as half the pair impedance.

Now, to create the transmission line structure on a conventional FR-4 PCB (in order to keep this stuff affordable!), we have several options. For differential traces, we have several options. Let's say your traces are on the top or bottom layer -- option one is edge-coupled microstrip (the picture I have is 'coated', where solder-mask is above it. Technically, there's edge-coupled coated, and edge-coupled surface for top/bottom layer options -- for really high frequency RF work, even the presence of solder-mask can be an issue).

Based on the distance to the return plane below it, the spacing between the two lines, and the width of each line, your PCB fab can deliver you a structure that presents the target impedance.

Now, let's say you're on an inner layer. The structure used here is generally edge-coupled embedded microstrip:

Similar to the first one, this one also factors in the distance to the nearest reference plane. A lot of designers favor burying their high-speed pairs on internal layers to benefit from the 'free' shielding of copper planes to reduce radiated emissions. Edge-coupled offset stripline is used when you have a signal layer sandwiched between two plane layers:

To get these differential structures, you contact your PCB fabrication house and tell them the differential impedances you're looking for -- this is part of the PCB stack-up design process. The fabrication house runs the actual materials they use (which have differing Er values) for cores and pre-preg materials, and come back to you with a set of geometries to follow in your design tool, e.g. (not real numbers) "0.2mm thick traces with 0.15mm spacing on Layers 1 and 8 for 100 Ohm impedance +/- 10%". You then input these values into Altium, and it will intelligently make sure that when you route pairs you've called out as differential that they follow those geometries.

By design, when you fabricate your PCB with your shop and send them the stack-up that has been designed, those traces will result in the desired characteristic impedance. You should request an impedance coupon, which is generally a piece of your PCB from the outer portion of the array where a duplicate structure of the transmission line has been created, and a TDR (time-domain reflectometer) is used to provide you the actual impedance constructed. Typical tolerance is around 10%.

Length-matching does not affect the differential impedance and differs from protocol to protocol. There is intra-pair skew (P to N), and inter-pair/inter-lane skew (i.e. from PCIe Tx Lane 0 to 1) skew, where the latter is generally more tolerant of mismatch than the former. This is something you generally analyze near the end to add meandering or serpentine routing to get the members of the pair to meet the manufacturer specification. I use a script that dumps the raw net lengths to Excel, and then conditional formatting to let me know how I'm doing in meeting spec (redacted somewhat -- this is a board with a module that has some mis-match, and a carrier PCB that has mis-match):

And here is an example of Altium set-up for 100 ohm differential pairs based on my vendor's recommendations:

Here are some other tips I've picked up along the way that may help you out in no particular order:

• Given a tolerance for mis-match from a manufacturer, start out by halving it if possible. In a case like PCI Express where you have a host PCB and a carrier PCB, this (sort of) splits the tolerance between the two.
• When fabricating a board with differential impedances, use "D-Codes". Use the hundreths or thousandths digit in trace widths to differentiate between different impedances. For example, if 0.20mm was called out as the width for both 90 ohm and 100 ohm, I would make 90 ohm 0.201mm and 100 ohm 0.202mm, and add fabrication note explaining what I did. The CAM engineer can then easily pick out the pairs using his software and do what he needs.

So, before you start your next PCB project with protocols / requirements that imply differential trace routing:

1. Identify all the different impedances to be controlled, and what layers they will be on (i.e., what are your signal layers).
2. Contact your fabrication house with the above information and work with them to define a stack-up for your project and get the required geometries. Alternately, as stated in the comments below, with the appropriate material and other information, your EDA tools might be able to provide you with the required geometries.
3. Set-up your CAD tool with the appropriate rules based on the numbers from step 2.
4. Define net classes for the pairs and route away!
5. Utilize a script or similar to generate a report that shows intra-pair/inner-pair mismatches and whether they are within spec or not.

You may be trashing the ADC's VDD lines or REF lines, or trashing the sampling clock (causes jitter, ruining the noise floor).

Assuming 1mm by 100micron coupling area (parallel-plate model) with 100micron spacing, and ER=5, the capacitance is C = E0*Er*Area/Distance. The 100micron / 100micron cancels, thus C is 1e-11F/meter * 5 * 1mm = 50 femtoFarads. With 1nanosecond edge to the LVDS, and 0.2v swing, or 0.2v/nS, the induced current is (I = C*dV/dT) = 50e-15F * 0.2v/1e-9s = 50 * 0.2 * e-15 e+9 or current is 10*e-15+9 = 10e-6 =10uA with rise time of ?? 100 picoseconds? Into bypass caps with 1nH inductance, the upset voltage is V=L*dI/dT or V_cap_upset = 1nH * (10 * 1e-6)/100pS == 1e-9 * 1e-5/1e-10 = 1e-14 * 1e+10 V_cap_upset = 100 microVolts. Can you live with that, occurring on EVERY BITTIME of the LVDS?