From the outside, each memory chip is organized as 1M words of 1 bit each, which means that it takes 20 address bits to specify a word.
Internally, the memory is physically organized as a square matrix of 1024 rows and 1024 columns, with one bit in each position in the matrix.
There are at least two reasons that the physical organization is important to the question:
The memory chip only has 10 address pins. The full 20-bit address is fed into the chip in two stages, the 10-bit row address first, and then the 10-bit column address.
When a refresh operation occurs, an entire row is refreshed all at once.
In some cases it is possible to replace DRAM with SRAM, by adding some logic to latch the row address. Whether this will work in a particular circuit depends on the timing of the RAS, CAS, and /WR signals and how the SRAM responds to them. 1 bit DRAMs have separate data input and output pins. If these are not tied together in the circuit then you may also need a Tri-State buffer to bridge between them. Getting the timing right could be tricky.
Here are two examples that work:-
SRAM replacement for lower 16K ← ZX Spectrum
SRAM replacement for TMS99x8 VRAM
You may be able to use higher capacity DRAMs provided that they are compatible - compare their data datasheets to make sure. The main things to watch out for are RAS/CAS timing (Fast Page Mode, EDO etc.) and refresh requirements.
However replacing the the faulty DRAMs with correct equivalents would be much easier and more likely to succeed. Although these older DRAMs are no longer manufactured, many are still available on the second hand market - usually selling at much cheaper prices than when new.
You may not have found what you want because you haven't searched all the equivalent part numbers. eg. '41464' is equivalent to '4464'. Here are some selling on eBay right now:-
D41464C-10 NEC DIP18 10NS
5PCS KM41464AP-12
Just be aware that these chips may be refurbished and possibly remarked with different parts numbers. Usually they are equivalent, but sometimes not (I bought some 'MCM2114P20 1kx4 SRAM' chips that are actually BU2114F 8 bit shift registers!).
Best Answer
DRAM is organised in a multi-level hierarchy, and knowing the correct terminology for the various layers is key to making sense of it, so I'll briefly recap them to make sure we are on the same page. (This is obviously only talking about the straightforward textbook case, and not considering things like ECC.)
On the lowest level, there is the bank, which is the physical 2D array of cells (capacitors/access transistors) and the word lines and bit lines connecting them. There is one row buffer per bank, which is followed by a column decoder to select – indeed – only one bit from the row.
Eight banks per chip makes for eight data output pins per chip. Eight of these chips would then be combined to make up a rank with 64 output bits. In the case of DIMMs, each physical memory module consists of at least one such rank. For multiple-rank DIMMs, the chips that make up the different ranks share the same command and data lines, so only one rank can use the bus at any moment in time (there are chip-select lines to address them).
Finally, a channel describes the complete system of one or more ranks and the command/data busses connecting them. As far as the low-level signalling is concerned, each channel is an entirely separate bus, so different accesses never conflict, etc.
As to your question about selecting only a single byte: The memory controller is free to handle those 64 bit chunks of data in whichever way is the most appropriate. In theory, it could just include a mux to select the appropriate byte of data to read. In modern processors, however, all memory accesses are typically done in units of cache line width (64 bytes) anyway, so all the bits would be forwarded to the cache subsystem. Even if only reading one byte into a register, the whole cache line would be fetched first.