I suspect the problem is that you need to control the data enable line with the microcontroller. Set it high at reset. Then, set it low right before (more than 100 ns) you start transmitting data. After the 35 bits, bring it high again.
Also, the datasheet explains the missing 35th pin you were wondering about in Note 1 on page 1. In the MM5450, it is replaced by the data enable line.
According to David Harris's presentation for eve224a course: (slides 6-11 and 47)
Delay d = f+p = g*h+p
Where d is process-independent delay, f is effort delay (stage effect), p is parasitic delay, g is logical effort, h is electrical effort (fanout; h = C_out/C_in)
In the Wikipedia article "Logical Effort" there are some examples too:
Delay in an inverter. By definition, the logical effort g of an inverter is 1
Delay in NAND and NOR gates. The logical effort of a two-input NAND gate is calculated to be g = 4/3
For NOT gate with FO1 (driving the same NOT gate):
g=1; h=1; p=1; so d = 1*1 + 1 = 2
For NOT gate with FO4 (the FO4 metric itself):
g=1; h=4 (Cout is 4 times more than Cin); p=1 so d = 1*4+1 =5 (the same result is at page 20 of books "Logical Effort: Designing Fast CMOS Circuits", draft from 1998)
1 FO4 delay is equal to 5 process-independent units (defined by harris, slide 6)
For NAND gate with two inputs (p=2) which drives the same:
g=4/3; h=1; p=2; d= 4/3 * 1 + 2 = 10/3 = 3,3 (a 1.5 times slower than NOT with FO1, but faster than NOT FO4)
For NAND gate asked by me - 2 inputs which drives 3 same NANDs:
g=4/3; h=3; p=2; d= (some magic inside) 4/3 * 3 + 2 = 6
So
Delay of 1 FO4 gate is equal to 5/6 delay of NAND (2-in, 3 FO).
The last problem is to convert chain delay of 18 NANDs to chain delay of FO4. (slide 41 of harris)
Hmm.. seems I need only to multiply 18 NANDs delay with 6/5... 21,6 FO4.
Thanks!
Best Answer
As long as you observe the datasheet limits (as you seem to have done) there are no real tricks here. A typical microcontroller may contain thousands to millions of transistors so tend to be fabricated using processes suited to to higher density logic instead of being aimed at high-current / power dissipation.
Those simple gates / drivers might contain in the order of dozens of transistors so use different processes, so if you find a part where the datasheet meets your needs go for it.
Just as a further comment, in high-volume commercial designs sometimes the reason the 'trick' isn't used is that when machine placed the transistors and a few resistors often work out cheaper.