Electronic – FIltering a PWM signal

Here's a circuit I did a few years ago that demonstrates a driver chip local to the MOSFET and an over-current protection in case the load shorted out. The MOSFET used is not as suitable as the BUK954 you mentioned on another question. I'd use that type for your job.

The load is assumed to be purely resistive. In fact the original circuit had two MOSFETs driving a transformer with a centre-tap to the positive supply rail and it didn't need fly-back diodes (it used snubbers) but your's might need a protection diode across the load.

Circled in red is a local +5V power rail used for the over-current monitor - this can easily be derived locally with a small linear regulator such as 78L05.

Also note the big array of capacitors to the left of the circuit that absorbs most of the transient energy locally produced by switching the load. The original design was switching at 600kHz so if you wanted to run faster than 20kHz this shouldn't be a problem but i wouldn't go above 100kHz for the sake of efficiency.

When it is charging (input to the transistor low), it is charging towards 10V through a resistance of 6.45K ohms (the Thevenin equivalent source resistance of the divider plus the 4.7K resistor), and when it is discharging (input to the transistor high) it is discharging through a resistance of 4.7K ohms (to maybe 50mV- the VCE of the saturated transistor- it won't make much difference so I'll guess at it- you can refer to the datasheet for a slightly better value).

For steady state, assume the voltage is fixed (does not change during a cycle), so we know the current charging must equal the current discharging if the times are equal (ask if that is not obvious).

So (10 - Vc)/6.45 = (Vc - 0.05)/4.7

solving, Vc = 4.244V. (Even worse!)

I don't know where the value in your simulation comes from but there will be lot of ripple in the voltage with such a small capacitor. Figure about 0.001 second * 0.9mA/10^-6 = 0.9V, so +/-450mV ripple (about 10%), so perhaps it's the peak voltage, not the mean-> 4.244 + 0.45 = 4.694, which agrees with your simulation.

You can use a more symmetrical drive either by increasing the 4.7K to a much higher value or using a CMOS buffer that will also get rid of the Vce(sat) term. Just remember that the buffer does not make this issue magically go away, and if you have a relatively low resistance compared to the buffer output impedance, and that impedance is asymmetrical (as it usually is) you may not see the exact voltage you're expecting.

Note that using a highly asymmetric switch like this one introduces a significant nonlinearity, which may be undesirable. In this case, it's about -15% of signal at mid-scale or -7.6% of full scale.