Electronic – Scaling 12V PWM signal to 0-10V

pwmvoltage divider

I'm trying to translate a 3.3v PWM signal through an optocoupler to the 12V side of a circuit, filter it to obtain a relatively clear DC voltage, and scale that to 0-10V for a control element.

So far, my circuit looks like this:

enter image description here

The square wave gen is emulating the PWM signal, the resistive divider should scale the voltage from 12V to 10V and the RC filter should re-create the variable DC voltage from the PWM signal.

What I'm experiencing though, is that at 50% duty cycle, the filtered output is not 5 volts as expected, but slightly lower, at 4.69V.

What is the source of this inaccuracy?
What do i need to take into consideration to make a reliable linear output?

Please advise!

Thanks in advance,
-S

Best Answer

When it is charging (input to the transistor low), it is charging towards 10V through a resistance of 6.45K ohms (the Thevenin equivalent source resistance of the divider plus the 4.7K resistor), and when it is discharging (input to the transistor high) it is discharging through a resistance of 4.7K ohms (to maybe 50mV- the VCE of the saturated transistor- it won't make much difference so I'll guess at it- you can refer to the datasheet for a slightly better value).

For steady state, assume the voltage is fixed (does not change during a cycle), so we know the current charging must equal the current discharging if the times are equal (ask if that is not obvious).

So (10 - Vc)/6.45 = (Vc - 0.05)/4.7

solving, Vc = 4.244V. (Even worse!)

enter image description here

I don't know where the value in your simulation comes from but there will be lot of ripple in the voltage with such a small capacitor. Figure about 0.001 second * 0.9mA/10^-6 = 0.9V, so +/-450mV ripple (about 10%), so perhaps it's the peak voltage, not the mean-> 4.244 + 0.45 = 4.694, which agrees with your simulation.

You can use a more symmetrical drive either by increasing the 4.7K to a much higher value or using a CMOS buffer that will also get rid of the Vce(sat) term. Just remember that the buffer does not make this issue magically go away, and if you have a relatively low resistance compared to the buffer output impedance, and that impedance is asymmetrical (as it usually is) you may not see the exact voltage you're expecting.

Note that using a highly asymmetric switch like this one introduces a significant nonlinearity, which may be undesirable. In this case, it's about -15% of signal at mid-scale or -7.6% of full scale.

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