Electronic – Fixed Point Division in verilog for Spartan 6

1. Is there any documentation for that is generic or covers Spartan-6 LX9 board?

   The DCM is fully contained within the FPGA chip. So it doesn't matter what board you have. The documentation will be based on what chip you have.

   For the Spartan-6 family, see the Spartan 6 Clocking Resources User Guide

2. Is using this module is absolutely necessary in this example? Is that possible to do the same thing easily w/o using that module?

   If you're just blinking LEDs, you probably don't need to use the DCM. Probably they used it because its a very complicated block and they specifically wanted to provide an example of using the DCM without much else in the way of complex logic to confuse things.

3. How people usually go about vendor specific things like clock? For example, if one wants to target both Altera FPGAs and Xilinx ones. What is the process to achieve that? Is it similar to ordinary C pre-processor typedefs etc?

   Unfortunately, complex hard cores like clock management is one of the areas where there's not much compatibility between vendors. You'll likely have to make significant code changes if you want a design using these features that is portable between two device families, whether they're from the same or different vendors.

   If you can simplify your interface so that you just have one input clock coming from off-chip, and a number of derived clocks that are distributed to the rest of your logic, the cleanest solution is probably to push all of the vendor-specific code into a single module that you can instantiate in your top-level code. Then you can just use a different "clock management" module depending which device you're targeting.

   If you want to do something like dynamically changing the phase relationship between various clocks, or switch between several choices of reference clock frequency, you probably have no choice but to re-code substantial chunks of logic for different target devices.

   Remember that in addition to the Verilog code, there will probably also be numerous constraints that need to be defined, and these will also need to be different for different devices.

Basically what it is saying is that there is a fast path (a direct connection) from certain pins into the DCM but for some reason this fast path can't be used. This could be for a number of reasons. If I'm reading the datasheet right, P53 isn't a clock capable pin so there won't be a fast path. You can also get problems if you've LOC'd the DCM to the wrong site in the UCF or you are using many DCMs such that the ideal site isn't available. Looking at your project though, it looks like this is the only thing in the design?

Where did you get the PAD53 constraint for the input clock?