Spartan 3AN FPGA DCM

fpgaspartanverilogxilinx

While I use the internal clock for DCM clkin input I am getting clk0 as perfect frequency of output same as internal clock but not in remaining o/p pins. I changed from previous coding like this and also schematic as below.

module dcm_clockverilog(clk,rst,clkdiv,clk0,clk2x,locked,clock);

input clk;
input rst;

output clkdiv;
output clk0;
output clk2x;
output locked;
output  clock;

wire clk0;
wire clk2x;
wire locked;
wire clkdiv;


reg [7:0] count=0;
reg clock=0;

dcmm instance_name (
    .CLKIN_IN(clock), 
    .RST_IN(rst),  
    .CLKDV_OUT(clkdiv), 
    .CLK0_OUT(clk0), 
    .CLK2X_OUT(clk2x), 
    .LOCKED_OUT(locked)
    );

always @(posedge clk)
begin
   count <=count+1;

if(count<=9) 
   clock<=0;
if(count>=10)
   clock<=1;
if(count>=19)
   count<=0;    
end 

endmodule



//---------------------------------------------plan ahead 

# PlanAhead Generated physical constraints 

NET "clk" LOC = P57;//-- (GCLK)
NET "clk0" LOC = P7;//--(I/O)
NET "clk2x" LOC = P8;//--(I/O)
NET "clkdiv" LOC = P10;//--(I/O)
NET "clock" LOC = P11;//--(THIS CLOCK I ASSIGN AS INPUT FOR DCM CLKIN) )
NET "locked" LOC = P12;//--(I/O)
NET "rst" LOC = P18;//--(INPUT SWITCH)

enter image description here

Best Answer

You don't have CLKFB connected - I'm surprised you get anything!

From the Spartan 3 userguide, UG331

CLKFB Clock feedback input to DCM. The feedback input is required unless the Digital Frequency Synthesis outputs, CLKFX or CLKFX180, are used stand-alone. The source of the CLKFB input must be the CLK0 or CLK2X output from the DCM and the CLK_FEEDBACK must be set to 1X or 2X accordingly. The feedback point ideally includes the delay added by the clock distribution network, either internally or externally.

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