I have basic knowledge in static timing analysis. I understand concepts about setup and hold time of bistables and that failure to meet these two timing constraints can lead to metastability where output of such bistables can become unpredictable (as transients have not died).
What are different techniques to address issues of setup and hold time violations for FPGA's and ASIC designs ?
Best Answer
This answer is more geared to an ASIC than an FPGA, but some will still apply.
To address setup time violations, you can:
For hold time violations: