Electronic – FPGA SDC timing constraints, understanding output delay

fpgasdctiming-analysis

I'm having a little bit of trouble understanding the timing convention of an SDC command:

set_output_delay 1.0 -clock_fall -clock CLK2 –min {OUT1}
set_output_delay 1.4 -clock_fall -clock CLK2 –max {OUT1}

Does this mean that after the launch clock (CLK2 falling edge), the output signal (OUT1) is allowed to transition between these min/max windows (signal edge occurs somewhere beteen 1.0 ns and 1.4 ns after the falling edge of CLK2)?

So is it basically the inverse of describing where a signal will needs to be valid: where it is allowed to transition/describe where the signal can be invalid?

Is my understanding correct?

Best Answer

No, these constraints don't mean that OUT1 has to transit in that timing window. The output delay is modelling the delay between the output port and an external (imaginary) register.

Delay of the path through OUT1 can be thought as follows.

t_total_delay = t_clk-to-Q + t_comb_delay + t_output_delay - t_clk_skew

The maximum value of t_output_delay (1.4 ns) is simply used for setup time and the minimum value (1.0 ns) is used for hold time.

Let's think about setup time. OUT1 has to transit 1.4 ns before (or earlier) the falling edge of CLK2. Say your clock period is 10 ns and the source register is also negedge triggered. In case t_clk_skew is zero, t_clk-to-Q + t_comb_delay has to be lower than or equal to 8.6 ns (10-1.4) to be able to meet setup time.

For hold time, t_total_delay has to be greater than zero. The critical part here is the clock skew. If t_clk_skew is very small, it is very easy to meet hold time. Even only t_clk-to-Q is usually greater than library hold time, however we don't need library hold time here, because the path is not going to a real register.

If we want to consider that library hold time, we can set a smaller output delay. It is also very common to set a negative value to be on the safe side. For example:

set_output_delay -1.0 -clock_fall -clock CLK2 –min {OUT1}

Related Solutions

Electronic – Understanding timing constraints

Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer.
Choose File > New SDC file. The SDC editor opens.

Type the following code into the editor:

create_clock -period 20.000 -name osc_clk osc_clk
derive_pll_clocks
derive_clock_uncertainty

Save this file as my_first_fpga_top.sdc (see Figure 1–38).

Electronic – MT9M001 to FPGA input timing

The half period is not 10.416 ns at worst case. Since the minimum clock duty cycle is 45%, the half period should be lower than 9.374 ns (20.833*0.45). If we consider clock rise/fall time too, 9 ns for min(t_LVS)+max(t_PLH) makes sense.

In case LINE_VALID is captured by a negedge-triggered flip-flop, the bottleneck is min(t_LVS). It can be constrained as below. LINE_VALID rises 2 ns before PIXCLK falls.

set_input_delay -max -2 -clock cam_pixclk_virt -clock_fall \
    -rise [get_ports LINE_VALID]

In addition, LINE_VALID falls 13 ns (t_PLL) after PIXCLK rises.

set_input_delay -max 13 -clock cam_pixclk_virt \
    -fall [get_ports LINE_VALID]

Actually these constraints will not prevent the line lengths from getting messed up. We don't know min(t_PLL), so LINE_VALID has a possibility to fall near the negedge of PIXCLK and it may get metastable. This issue should be handled functionally.

One solution would be using posedge of PIXCLK instead of negedge. If DATA is constrained enough for minimum input delay (it's -1 in your constraints), all signals will be safe to capture at posedge.

Best Answer

Related Solutions

Electronic – Understanding timing constraints

Electronic – MT9M001 to FPGA input timing

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