computer-architecturedigital-logic
I hope this is the place to ask such a question.
Given a shift register- within 8 clock pulses 8 bits will enter this register, I need to make a circuit with this register, and other 3 flip-flops such that its exit line would be 1 if the first 4 bits are equal to the last 4.
This is an example of possible solution.
My question for you is: How come that only at the end of the 8th pulse a value would go out to the "equal" line? (or that in this solution- successes consider as output of "1111"?)
Serial/parallel-load shift registers and bit rotations are going to work most naturally with a D flip flop, since they just send data straight through; binary counters are going to work most naturally with a T flip flop, since each counter bit Ck = Ck,previous XOR carryk, where carry is the carry bit from the previous stage.
If you look at JK flip-flops, however, they are the "universal" flip-flop that can act as a D- or T- flip-flop depending on the input signals.
To get a D from a T, or vice versa, you need an XOR gate. To get a T from a JK, you just tie the JK inputs together. To get a D from a JK, you need an inverter, as the J/K inputs need to be opposites.
In your application, you've got enough complexity, that I suspect the gate counts are going to be very close, and it's probably not worth worrying about -- unless you have to optimize, in which case you'll just have to try it for each case.
IMHO, the D flip-flop is conceptually the simplest to use, and it works naturally with most of your operations, so I'd start with that.
There may have been a wire in the wrong place or something. I did have it spread across three breadboards. I sketched everything out in a schematic, then pulled all the wires out and started over, following the schematic. Then things worked! Here's the schematic I used. The LED only lights up once the D input to the first flip-flop has gone HIGH and then LOW, which is how it should work.
Best Answer
What exactly are you given to work with? Your diagram shows some gates in addition to the shift register and the flip flops. If the shift register bits are all exposed, you could simply use four XOR gates and a quad OR or NOR gate. No flip flops required. Otherwise, do you need to know, at any given time, whether the last four inputs match the previous four, or will you only need to ascertain that every four clock pulses, or every eight, or what?
Conceptually, I think your best bet may be to use your flip flops to make a counter which will increment up to a max of four whenever the input to the shift register matches the signal four previous, and will reset to zero otherwise. Without understanding the exact requirements, though, it's hard to say for sure.