How closely do you pack your thermal vias? I know that more vias divides the amount of heat each via can move and that smaller vias allows more vias to be packed together. Knowing this, it seems like more vias are better for thermal dissipation.
There are diminishing returns for the amount of vias that are placed, but assuming that you can place as many as you want without accruing extra manufacturing costs, how many vias can you place before compromising the structural integrity of your board? (assuming using the standard fr4 board substrate at a standard 1.6mm thickness)
Should they be placed in a pattern? What do you do personally? Does everyone just choose a target amount of watts to dissipate through the board from the junction and make the minimum amount of holes?
Best Answer
I use this document by Cree as reference. They provide some measurements, and from these measurements I make some ballpark assumptions.
It has multiple scenarios considering different via sizes, PCB thickness, amount of vias, etc.
Note that these are "Solder point through board" Thermal resistance measurements, so I believe they do not account for heat dissipated through a larger copper plane, just transfer through the board.
Also, the size of the device will probably influence a lot the amount of vias that are effective, since packages with thermal pads will help a lot lateral heat carry, making move vias more useful, so this is mostly valid for devices about the size of these LEDs.
This chart would indicate that for 1.6mm FR-4, 15 ~0.4mm vias seem to be the point after which larger vias and/or more of them give diminishing returns.
This next chart seems to indicate that around 4mm trace width (that is, something like a ~4mm thickness ring around a heat spot, see figure 12 and 13), the PCB loses a lot of capacity to transfer heat laterally:
In their recommended layouts for LEDs, they use 0.254mm vias spaced 0.635mm apart.
If you put 16 0.4mm vias in a 4x4mm square rectangle (larger distances would hinder lateral heat transfer drastically), this would give a maximum pitch of 1mm. The minimum pitch would be the minimum inter via distance + your desired margin.
There are other documents (such as this one by on semi) that cover PCB plane size for different layer counts. Arguably they provide diminishing returns around ~40mm for multilayer boards. (I believe its less for 2 or single layer boards due to lower lateral heat transfer capacity).