In terms of interfacing to the camera and clocking data in, that will be fine it can handle it. It may not handle the speeds you are interested in.
5MP * 3 (colours, RGB) * 15 (times per second) = 225*e6. (assuming 24 bit colour depth)
So that means you will need a clock speed of at least 225 MHz assuming you can move data on every clock signal, which you may not, depending on the sensor, so you may need to double this figure to circa 450-500 MHz
The Spartan you are looking at has a clock signal of 50MHz.
So the short answer is no, not at those speeds.
The other consideration you need to apply is how many logic blocks does your logic require? to work this out, write out your implementation in VHDL/verilog, simulate and then synthese. Read the outputs from the tool and it will tell you how many logic blocks you need, then select an appropriate FPGA which has 50% more logic blocks to allow for unuseable blocks due to routing constraints and gives you some room to grow.
Also you need to consider RAM or some other sort of memory and how your will store these bursts. If you are shooting at 15 fps for 1 second then you need 225 MB which is a lot or RAM for an embedded system.
After storing in RAM you will need to flush into ROM of some sort (for example compact flash).
Long, parallel traces. No signal termination. No decoupling caps on the RAM. Signal traces going from top to bottom layer without a cap near by. Traces with long, unterminated, stubs. Some signals going through 5 vias. And possibly not enough vias on the power/gnd pins of the BGA (but it's hard to tell from your picture).
Any of these could cause memory problems, and some at any speed. Carefully probe your clocks at the destination with a high speed o-scope (350 MHz or greater) and show us what you see. Odds are that you have a problem with signal integrity.
Best Answer
Given the lack of detail in your question, here is a brief generic overview.
SDRAM, like SRAM, is a memory. To write to it, you present an address and some data, and to read from it, you present and address and get some data back some time later.
However, unlike SRAM, SDRAM requires both initialization/configuration at startup as well as ongoing refresh activity in order to operate correctly. Also, the internal structure imposes a multi-level addressing scheme involving banks, rows and columns. All of this means that you need to have a controller for the SDRAM inside your FPGA that manages all of these activities while working within the timing and sequencing rules imposed by the SDRAM chip. This controller generally takes the form of a fairly complex state machine that runs at the same speed as the SDRAM interface.
Xilinx provides a SDRAM controller generator as part of its design toolchain, and in some FPGAs, there is a dedicated, or "hard core" memory controller.