Electronic – How do cheap Raspberry CSI-2 cables get around differential impedance matching

If you remember that a differential signal is really just two single-ended signals that happen to have signals that change in the opposite direction at the same time, it's fairly simple to see what to do.

1) Make sure you have half the differential impedance between the individual traces and the reference plane below. For LVDS that would be 50R trace impedance. Notice that distance to the other trace in the pair as well as other Cu will impact the impedance. Use a 2D field solver to do this (The best free tool I have found is TNT).

2) Make sure you don't have too much crosstalk between any traces (this includes crosstalk between the two traces of that pair, although this is often not much of an issue - see note below).

Yes this may be contradictory advice to what you may read in some app notes, but do your own research in books like the two excellent books on signal integrity by Lee Ritchey (you can legally get the first one "Right the First Time, volume I" as a free or cheap download on the net).

Note on #2: You will (obviously) also have crosstalk between the two traces of the pair. And at just the point where the signals switch (both signals switch at the same time). The end result of that is a degradation of the edge rate.

Now if you follow advice #1 you will have more than plenty spacing between the two traces that this will normally not be a problem for your circuit. Actually most often analysis show that this is not a likely issue. It is just mentioned here for completeness.

Does this help you? I will be happy to expand the answer.

Ok, so I think that I have at least some idea now:

• Considering the 100 MHz signaling frequency, the data and clock signals need to run over transmission lines (assuming a propagation speed through copper of 0.6c, the wavelength is ~1.8m, and using the 10% wavelength rule of thumb and the fact that there is probably higher frequency content in that 100 MHz base signal, it's right in that range).
• In order to minimize signal reflections and other distortions in the line, impedance needs to be as consistent as possible throughout the line. At the frequencies that make it a transmission line, the impedance of the line is dominated by reactance, and more specifically, by the ratio of inductance to capacitance.
• I'm assuming that the inductance of a trace on the PCB will be largely constant for a given length regardless of the layout (excepting funky routing), so the impedance has to be controlled by adjusting the capacitance, which is managed by moving the signal lines closer to or further from the ground plane and/or traces.
• The ground plane is absent under the card edge for three reasons:
  1. The signal pins are wider than the traces, which would result in a higher capacitance between them and the ground plane.
  2. The ground pins add capacitance to the line.
  3. The PCIe connector is built to have the proper impedance as-is, and placing a large ground plane right in the middle would throw off the capacitance, and therefore the impedance.
• I think that the ground pins between the signal pins probably help to reduce crosstalk, but maybe that is a secondary concern?

Am I anywhere close to the right answer, or am I way off? I had looked at transmission lines multiple times and couldn't figure it out, but this answer kind of just came to me after paying more attention to the formula for determining characteristic impedance.