First thing you need to recognize is that designing with a 16-bit ADC is not trivial. Even at 1 sample/s, you need to pay extreme attention to every aspect of the design to achieve 16-bit precision, or even more difficultly, 16-bit accuracy. At 130 MSa/s, everything is even more difficult.
The parts you need to do this kind of design simply won't be inexpensive. First, because of the extreme precision and careful testing needed to achieve the required performance. Second, because this kind of thing isn't done in mass-market products, so the parts aren't built in the kind of extremely high volumes that can bring the price down for everyone.
As Dave says in another answer, be sure you really need 16 bits before you go down this road. But maybe you really need 12-bit precision, and you know that if you use even a 14-bit ADC you're going to have a hard time achieving that, so you're designing with 16-bit ADC and optimize everything else as much as you can.
Another key is likely to be understanding exactly what specs you need to make your system work, and don't over-specify your clock jitter. In an SDR application, you're going to be doing math on the samples to extract specific frequency bands, etc, which will have an averaging effect over many cycles. So you might not care too much that absolutely every sample is timed perfectly, only that over your calculation interval, there isn't too much deviation from ideal timing. How much is too much, of course, depends on what kind of math you're doing and how small a signal you need to extract from how much noise.
CTS Valpey, for example, has XO's with rms jitter specs as low as 200 fs. But this spec is defined when the phase noise is integrated over a specific frequency band, 12 kHz to 20 MHz (relative to the carrier). If the total cycle-to-cycle jitter is considered, the spec jumps to 3-6 ps, depending on the center frequency.
Let me also address one comment you made in your question:
OCXO are extremely stable over time ( years ) and are usually used for that.
The "ovenized" part of that product mainly reduces the drift due to temperature change in the surrounding environment, which can be significant over time scales of minutes or seconds, not just years. It will also reduce wear on the part due to thermal cycling and improve the stability on a time scale of years.
For the < 100 fs jitter range you're looking for, you might actually need an OCXO to prevent small temperature changes affecting the performance during the time it takes to measure the jitter accurately enough to know you've achieved your spec.
I read somewhere [...] that the real limiting factor being electron travel speed in the circuits, which wont be met until extremely high THz rates, or well over PHz.
Pure fiction. Electron travel speed itself is relatively low. Electromagnetic wave travel speed - that is the interesting one - is in the order of the speed of light. At 1 THz - or in 1 ps (picosecond, 1e-12s) - your signal would travel just 0.3mm.
what would prevent me from speeding up a CPU if I replace the clock
The critical path would prevent you from going above a certain frequency that is usually not much higher than specified. In a nutshell this is the signal path that takes the longest time, but must be finished in one clock cycle. Once you rise the clock speed above that limit, the CPU will no longer operate correctly.
Best Answer
This is done using a device called a phase-locked loop, or PLL. Here is a block diagram of a basic PLL:
simulate this circuit – Schematic created using CircuitLab
The oscillator on the motherboard does not run at the CPU clock frequency, instead it runs at a frequency on the order of 100 MHz. This oscillator serves only as a known, stable reference frequency. Inside the CPU, the actual clock frequency will be generated by a voltage-controlled oscillator, or VCO. The VCO can be tuned to generate frequencies over a relatively wide range, but by itself it is not particularly stable or accurate - for a given control voltage, the frequency will vary from part to part and with supply voltage and temperature. A phase-locked loop then serves to lock the VCO output frequency into a specific relationship with the reference frequency.
The outputs of both the reference oscillator and the VCO are divided by programmable dividers (with a factor of D for the reference and M for the VCO output) and then compared with a phase and frequency detector (PFD). The output of the PFD is filtered and used to drive the VCO. This forms a control loop known as a phase locked loop, because it serves to drive the phase of the divided VCO to equal the phase of the divided reference. At the input of the PFD, the frequency will be \$ f_{PFD} = f_{ref}/D = f_{out}/M \$. The result is an output frequency with a specific mathematical relationship to the reference frequency, \$ f_{out} = f_{ref} * M/D \$. As can be seen in this equation, the frequency divider at the output of the VCO has the effect of multiplying the reference frequency by its division factor. This is how a PLL can effectively generate much higher frequencies than the reference frequency.
For example, assume the reference frequency is 100 MHz, the reference is divided by 1 (D) and the VCO is divided by 30 (M). This would result in an output frequency of 100 MHz * 30/1 = 3 GHz. This relationship can be changed by simply changing the divider settings, which can be done in software via control registers. Note that changing the frequency on the fly may not as simple as just changing the divider values, the frequency must be changed in such a way as to ensure that the CPU does not see any 'glitches' or clock pulses that are too short. It may be necessary to use 2 PLLs and switch between them, or to temporarily stop the clock or switch to another clock source until the PLL stabilizes at the new frequency.
PLLs are used all over the place to generate precise, easily tunable frequencies from fixed, stable references. Your Wi-Fi card and Wi-Fi router use them to select the appropriate channel by generating what's called the local oscillator frequency, a signal used internal to the radio to upconvert and downconvert the modulated data. Your FM radio most likely uses one to enable software control over the receive frequency, enabling easy recall of different stations. PLLs are also used to generate the high frequency clock signals used to drive the serializers and deserializers for Ethernet, PCI express, serial ATA, Firewire, USB, DVI, HDMI, DisplayPort, and many other modern serial protocols.