Electronic – How do registers connect to CPU buses


I'm wondering what type of buffers/techniques are typically used for connecting a cpu register(flip flops?) to a cpu bus(data/address/control). Since there are many registers on a single bus, I know there has to be some kind of tristate mechanism but how do you specify which buffers should be floating?

Thinking logically, there should be some kind of register select bit along with a read/write bit that toggles which register is in use and what it is doing with the value. Even though this makes sense to me, I don't think it is practical to AND every register input with a register select or r/w bit.

I've been searching the internet for schematics or documentation and I can't find any solid information. Most cpu schematics are so complicated that I'm having a hard time making sense of them. Any help is greatly appreciated.

Best Answer

In some device technologies, registers are connected to a bus using three-state outputs. Such an approach does have some advantages, but it generally either requires that either there be some "dead time" between the moment one register releases the bus and the moment another register starts driving it, or else runs the risk that a device might start driving the bus before the previous device has fully released it.

In other technologies, this approach is avoided in favor of using nested multiplexers. If there are 64 registers that can output to a bus bit, the device might have eight 8-way multiplexers each of which accepts input from one register, and one more 8-way multiplexer which accepts input from one of the first eight. While this may use slightly more circuitry than the bus-based approach, it has the advantage that every signal throughout the system will be driven by exactly one device at all times.