Electronic – How does a structural architecture know which entity to use

componentsvhdl

So I'm following this tutorial in which they explain some basic VHDL by using a four bit adder as an example:

-- Example of a four bit adder
library  ieee;
use  ieee.std_logic_1164.all;

-- definition of a full adder
entity FULLADDER is
     port (a, b, c: in std_logic;
           sum, carry: out std_logic);
     end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
     end fulladder_behav;
     -- 4-bit adder

library  ieee;
use  ieee.std_logic_1164.all;
entity FOURBITADD is
     port (a, b: in std_logic_vector(3 downto 0);
           Cin : in std_logic;
                sum: out std_logic_vector (3 downto 0);
                Cout, V: out std_logic);
     end FOURBITADD;
architecture fouradder_structure of FOURBITADD is
     signal c: std_logic_vector (4 downto 0);
component FULLADDER
           port(a, b, c: in std_logic;
sum, carry: out std_logic);
           end component;
begin
           FA0: FULLADDER
                port map (a(0), b(0), Cin, sum(0), c(1));
           FA1: FULLADDER
                port map (a(1), b(1), C(1), sum(1), c(2));
           FA2: FULLADDER
                port map (a(2), b(2), C(2), sum(2), c(3));
           FA3: FULLADDER
                port map (a(3), b(3), C(3), sum(3), c(4));
           V <= c(3) xor c(4);
           Cout <= c(4);
end fouradder_structure;

I am trying to understand why the component part in the fouradder_structure has to redefine the ports used in the FULLADDER entity; they both contain the following parts:

port(a, b, c: in std_logic;
sum, carry: out std_logic);

I then read somewhere that component defines the interface that the fouradder_structure is expecting. That would explain why entity and component both need to declare the used ports, but then how does the fouradder_structure know to use the FULLADDER entity that was defined previously? Is it a naming convention?

TL;DR, how is the architecture fouradder_structure aware it has to use the entity FULLADDER?

Best Answer

If you don't specify which architecture an entity instantiation is going to use, it uses the most recently compiled architecture for that entity.

Personally I would use direct entity instantiation. To use this, delete the component declaration (component FULLADDER ...), and instantiate it thus:

FA0: entity work.FULLADDER(fulladder_behav)
port map ( ...

In this way you can easily see which architecture is being used, and you save yourself having to maintain a component declaration as well as the instantiation.

If you don't want to do this for some reason, look at using configurations.

Related Solutions

Electronic – Problem getting VHDL syntax correct

VHDL accepts the ISO 8859-1 character set, this is UTF-8.

Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.

Your comments aren't delineated by two dashes (e.g. --), your double quotation marks all need to be replaced with ".

After which the VHDL code analyzes.

There's no discernible reason why d3, d2, d1, and d0 can't be replaced with a bit_vector. There may uses with the present port interface in the book.

Formal ports are associated with actual signals in an association list. It's possible to associate individual elements of a vector with a base element.

Converting between non-closely related types can be done with conversion routines:

-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
    port(
    d3, d2, d1, d0: in bit;
    a, b, c, d, e, f, g: out bit
    );
end entity;
architecture seven_segment of bcd_7seg is
    signal input : bit_vector (3 downto 0);
    signal output: bit_vector (6 downto 0);
begin
    input <= d3 & d2 & d1 & d0;
    with input select
        output <= "0000001" when "0000",
                  "1001111" when "0001",
                  "0010010" when "0010",
                  "0000110" when "0011",
                  "1001100" when "0100",
                  "0100100" when "0101",
                  "1100000" when "0110",
                  "0001111" when "0111",
                  "0000000" when "1000",
                  "0001100" when "1001",
                  "1111111" when others;
-- separate the output vector to make individual pin outputs.
    a <= output(6);
    b <= output(5);
    c <= output(4);
    d <= output(3);
    e <= output(2);
    f <= output(1);
    g <= output(0);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bcd_tb is
end entity;

architecture foo of bcd_tb is
    signal d:  std_logic_vector (3 downto 0) := "0100";
    signal output:    std_logic_vector (6 downto 0);
begin
DUT:
    entity work.bcd_7seg
        port map (
            d3 => to_bit(d(3)),
            d2 => to_bit(d(2)),
            d1 => to_bit(d(1)),
            d0 => to_bit(d(0)),
            to_stdulogic(a) => output(6),
            to_stdulogic(b) => output(5),
            to_stdulogic(c) => output(4),
            to_stdulogic(d) => output(3),
            to_stdulogic(e) => output(2),
            to_stdulogic(f) => output(1),
            to_stdulogic(g) => output(0)
        );
end architecture;

You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.

Electronic – VHDL: Is there a tool that automatically generates the signals (for use in testbench) and a component instantiation if an entity is given

Emacs with VHDL mode can do that: set the cursor inside a entity, choose

VHDL-> Port -> Copy

then

VHDL-> Port -> Paste as Testbench

generates a testbench architecture with entity, architecture, signals, instance, clock generator and stimuli process. The testbench look and feel can be defined in the vhdl mode options:

| [-]-\ Group Vhdl Testbench
|     |--- Option Vhdl Testbench Entity Name
|     |--- Option Vhdl Testbench Architecture Name
|     |--- Option Vhdl Testbench Configuration Name
|     |--- Option Vhdl Testbench Dut Name
|     |--- Option Vhdl Testbench Include Header
|     |--- Option Vhdl Testbench Declarations
|     |--- Option Vhdl Testbench Statements
|     |--- Option Vhdl Testbench Initialize Signals
|     |--- Option Vhdl Testbench Include Library
|     |--- Option Vhdl Testbench Include Configuration
|     |--- Option Vhdl Testbench Create Files
|     |--- Option Vhdl Testbench Entity File Name
|     `--- Option Vhdl Testbench Architecture File Name

Best Answer

Related Solutions

Electronic – Problem getting VHDL syntax correct

Electronic – VHDL: Is there a tool that automatically generates the signals (for use in testbench) and a component instantiation if an entity is given

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