The following information is in addition to Igor's excellent answer.
From a C programming perspective, the interrupt handlers are defined in the cr_startup_xxx.c file (eg cr_startup_lpc13.c file for LPC1343). All possible interrupt handlers are defined there as a WEAK alias. If you do not define your own XXX_Handler() for an interrupt source, then the default interrupt handler function defined in this file will be used. The linker will sort out which function to include in the final binary along with the interrupt vector table from cr_startup_xxx.c
Example of GPIO interrupts from ports are shown in the demo files in gpio.c. There is one interrupt input to the NVIC per GPIO port. Each individual bit in the port can be enabled/disabled to generate an interrupt on that port. If you require interrupts on ports PIO1_4, and PIO1_5 for example, then you would enable the individual PIO1_4 and PIO1_5 interrupt bits in GPIO0IE. When your PIOINT0_Handler() interrupt handler function fires, it's up to you to determine which of PIO1_4 or PIO1_5 (or both) interrupts are pending by reading the GPIO0RIS register and handling the interrupt appropriately.
Manual seems to clearly say:
You need both MAMCR and MAMTIM
Without MAMCR 'it does not hunt'.
Without setting MAMTIM it appears to hunt randomly.
MAMCR
2 bits in MAMCR control what MAM operating mode is used.
The default setting = 00 which is MAM disabled.
01 partially enables MAM functions and
10 enables all MAM functions.
11 is for when you are feeling bored and wonder what colour smoke it will make. They provide it just to make you curious.
MAMTIM
3 bits in MAMTIM set flash access cycle count.
User manual around page 105 says:
7.1 MAM Control Register (MAMCR - 0xE01F C000)
Two configuration bits select the three MAM operating modes, as shown in Table 6–99.
Following any reset, MAM functions are disabled. Software can turn memory access
acceleration on or off at any time allowing most of an application to be run at the highest
possible performance, while certain functions can be run at a somewhat slower but more
predictable rate if more precise timing is required.
Changing the MAM operating mode causes the MAM to invalidate all of the holding
latches, resulting in new reads of Flash information as required. This guarantees
synchronization of the MAM to CPU operation.
7.2 MAM Timing Register (MAMTIM - 0xE01F C004)
The MAM Timing register determines how many CCLK cycles are used to access the Flash memory. This allows tuning MAM timing to match the processor operating frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash
accesses would essentially remove the MAM from timing calculations. In this case the
MAM mode may be selected to optimize power usage.
ADDED
Question:
ANSWER
I want to say, read the manual and user guide in detail and see what all the registers are said to do.
That is a VERY complicated IC and you must be prepared either to spend the time understanding it, or use something else.
I have never used this part - I am just used to reading data sheets. It says that if you set MAMCR it WILL work but, IF I read the user guide correctly, it will use the number of clocks per cycle based on MAMTIM contents which are not defined according to this.
They MAY have been defined somewhere else but you need to know this.
The default may work Ok BUT you need to know this.
Best Answer
This question seems to arise from a confusion between
ThreadvsHandlermodes andPrivilegedvsUnprivilegedmodes.To quote the Cortex M4 Technical Reference Manual:
Necessarily speaking, the processor would need to start out in privileged mode so that key setup configuration can be accomplished.
An operating system or stack sophisticated enough to make use of an unprivileged mode would then need to explicitly activate it to impose those restrictions on "user" code.
If no part of the code on a system manipulates privilege levels, then whole thing is running in privileged mode, just as it might on a simpler processor not offering a distinction.