First thing you need to recognize is that designing with a 16-bit ADC is not trivial. Even at 1 sample/s, you need to pay extreme attention to every aspect of the design to achieve 16-bit precision, or even more difficultly, 16-bit accuracy. At 130 MSa/s, everything is even more difficult.
The parts you need to do this kind of design simply won't be inexpensive. First, because of the extreme precision and careful testing needed to achieve the required performance. Second, because this kind of thing isn't done in mass-market products, so the parts aren't built in the kind of extremely high volumes that can bring the price down for everyone.
As Dave says in another answer, be sure you really need 16 bits before you go down this road. But maybe you really need 12-bit precision, and you know that if you use even a 14-bit ADC you're going to have a hard time achieving that, so you're designing with 16-bit ADC and optimize everything else as much as you can.
Another key is likely to be understanding exactly what specs you need to make your system work, and don't over-specify your clock jitter. In an SDR application, you're going to be doing math on the samples to extract specific frequency bands, etc, which will have an averaging effect over many cycles. So you might not care too much that absolutely every sample is timed perfectly, only that over your calculation interval, there isn't too much deviation from ideal timing. How much is too much, of course, depends on what kind of math you're doing and how small a signal you need to extract from how much noise.
CTS Valpey, for example, has XO's with rms jitter specs as low as 200 fs. But this spec is defined when the phase noise is integrated over a specific frequency band, 12 kHz to 20 MHz (relative to the carrier). If the total cycle-to-cycle jitter is considered, the spec jumps to 3-6 ps, depending on the center frequency.
Let me also address one comment you made in your question:
OCXO are extremely stable over time ( years ) and are usually used for that.
The "ovenized" part of that product mainly reduces the drift due to temperature change in the surrounding environment, which can be significant over time scales of minutes or seconds, not just years. It will also reduce wear on the part due to thermal cycling and improve the stability on a time scale of years.
For the < 100 fs jitter range you're looking for, you might actually need an OCXO to prevent small temperature changes affecting the performance during the time it takes to measure the jitter accurately enough to know you've achieved your spec.
Best Answer
The question is ill-formulated. Is this about a clock FOR the processor, or about MAXIMUM INTERNAL CLOCK in the processor? The tag "overclocking" seems to hint for the latter.
So, the clock FOR a processor is usually coming from a crystal-stabilized oscillator, from an external one, or from built-in.
The INTERNAL clock inside a processor is generated from a special unit called PLL - Phase Locked Loop, which includes a VCO (Voltage-controlled oscillator) as inseparable part. The idea behing PLL is well introduced in this Wikipedia article.
The design of VCO can vary, and I believe in most current processors it is based on idea of ring oscillator having variable voltage-controlled delay. Several ideas of modern VCO designs are illustrated in this lecture.
The VCOs in microprocessors usually run continuously at a pretty high frequency - several GHz. Then digital dividers (in reference and VCO channels) mix at a phase detector, which outputs analog voltage that controls the VCO, and the properly filtered feedback locks the frequency to one from a working set of internal frequencies. These frequencies are used in various technologies to align the execution speed of a microprocessor with manageable power consumption, dynamically.
To achieve the goal of several internal frequencies, the VCO must operate in certain linear range of frequencies, to get into the frequency lock defined by digital frequency dividers, so no, it doesn't operate at its maximum, but rather somewhere in between min and max.
Be aware that the frequency synthesis is one of the most challenging areas of electrical engineering, so you should note that the lecture level is 620, post-graduate level, far from 101.