Electronic – How does a PLL inside a FPGA work

Xilinx use the term DCM for their enhancement to what they used to call a DLL, or Delay Locked Loop.

This (DLL) was a tapped delay line fed from the original clock signal, by selecting different taps, you could get different delays on the output clock signal. As the delays are unpredictable, logic compared the outputs from different taps until it found which tap number gave a full clock cycle delay - it was "unlocked" until it found the right tap. Then it updated that tap number as the delays drifted (e.g. as the input frequency changed or the chip warmed up) then other delays (e.g. 90 degrees, 180 degrees, were computed from that.

So it provided vaguely PLL-like behaviour without any analog circuitry, which was difficult to achieve in their processes at the time. Downside was that the jitter spectrum was different from a PLL as the delay was always an integral number of taps.

If you cascaded DLLs or DCMs, the second one will probably work, but a third one may have dificulty locking up due to the jitter imposed by the others.

The DCM is based on the same idea but provides other functionality such as clock frequency multiplication.

Newer FPGAs offer both DCM (DLL) and PLL but I expect the DCM is still easier to produce.

The question is ill-formulated. Is this about a clock FOR the processor, or about MAXIMUM INTERNAL CLOCK in the processor? The tag "overclocking" seems to hint for the latter.

So, the clock FOR a processor is usually coming from a crystal-stabilized oscillator, from an external one, or from built-in.

The INTERNAL clock inside a processor is generated from a special unit called PLL - Phase Locked Loop, which includes a VCO (Voltage-controlled oscillator) as inseparable part. The idea behing PLL is well introduced in this Wikipedia article.

The design of VCO can vary, and I believe in most current processors it is based on idea of ring oscillator having variable voltage-controlled delay. Several ideas of modern VCO designs are illustrated in this lecture.

The VCOs in microprocessors usually run continuously at a pretty high frequency - several GHz. Then digital dividers (in reference and VCO channels) mix at a phase detector, which outputs analog voltage that controls the VCO, and the properly filtered feedback locks the frequency to one from a working set of internal frequencies. These frequencies are used in various technologies to align the execution speed of a microprocessor with manageable power consumption, dynamically.

To achieve the goal of several internal frequencies, the VCO must operate in certain linear range of frequencies, to get into the frequency lock defined by digital frequency dividers, so no, it doesn't operate at its maximum, but rather somewhere in between min and max.

Be aware that the frequency synthesis is one of the most challenging areas of electrical engineering, so you should note that the lecture level is 620, post-graduate level, far from 101.