A document states that:
Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking.
You can use the PLLs as follows:
- Zero-delay buffer
- Jitter attenuator
- Low-skew fan-out buffer
- Frequency synthesizer*
- Reduce the number of oscillators required on the board*
- Reduce the clock pins used in the device by synthesizing multiple clock frequencies from a single reference clock source*
- On-chip clock de-skew
- Dynamic phase shift
- Counters reconfiguration
- Bandwidth reconfiguration
- Programmable output duty cycle
- PLL cascading*
- Reference clock switchover
- Drive the analog-to-digital converter (ADC) clock*
I have used PLL only to generate more clocks. For this reason I do understand the uses marked with •. However, the rest are completely unknown to me. What do they mean and why would I ever need to use any of them at all?
Some extra descriptions of the other use cases/modes may help.
A zero-delay buffer is where the phase of the output clock and the phase of the input clock are identical. By using a feedback network it is possible to make a synthesized output clock (e.g. to an IO pin) match exactly with the phase of an input clock pin. This is useful for example to create a high speed clock for deserialisation.
Jitter is basically inaccuracies in the transistion times of clock edges. For example due to threshold voltage or temperature changes your clock might sometimes have a period of 100ns, but during other cycles it might be 99.99ns or 100.01ns.
For analog/digital conversion, jitter is particularly bad as it reduces the effective number of bits.
It is possible to use a PLL to reduce the amount of jitter in the clock signal by effectively acting like a narrow bandwidth filter. Though in other cases PLLs can introduce more jitter than they reduce.
You may need to create multiple clock signals to, say, feed out to multiple converter devices, or drive multiple transcievers. Ideally these should be in phase with each other - i.e. have a low skew. You can phase shift multiple output clocks individually to tune out the skew caused by propagation delays.
Same as above, but to compensate for routing delays within a chip - some parts of the logic might be further away than others, or have long delay paths, so it is useful to make multiple syncrhonous clock signals with slight phase shifts to compensate for skews.
For example to align an incoming serialised data stream, you may need to adjust the phase shift of a clock signal on the fly as part of a link training process.
PLL counters are used to generate the output clocks - you might have multiply and divide counters to allow generation of fractional clock frequencies.
Being able to reconfigure these counters allows you to change the frequencies on the fly.
Sometimes you might want a reference clock of one frequency, say 100MHz. Other times you might want something else, say 125MHz. You can adjust the bandwidth of the VCO filter to cope with different frequency ranges.
Sometimes a 50% duty cycle clock is not helpful - for example in SERDES hardware you might want a latch clock that is high for only one bit period (e.g. for an 8-bit serdes, 12.5% duty cycle might be helpful).
You might have a primary clock signal coming from some external source (e.g. PCIe reference clock). If that fails or is disconnected, there are times when it's useful to have a backup reference clock that you can switch over to allow you to continue running.
Alternatively, for test equipment in particular, you might have an internal 10MHz reference clock, but to sync with other equipment want to be able to swap over dynamically to an external reference.