This is a comment that I saw in another forum:
Like any other memory storage, it's divided into smaller units. These units can contain data individually or can be treated as a big single block of memory. So suppose your RAM is divided into 512 individual blocks. You need to access the 199th block. So a sequential approach is to start from one end of the memory and move towards the desired block. So if you started at the 1st block, you need to pass through 1,2,3,4,5,……,197,198 blocks before reaching the desired block no. 199. But Random Access means that instead of passing through all the blocks present between you and the destination, You can directly access the desired block. Thus the time required to read any particular block remains constant regard less of its number, that is its relative position in the chip. Hence, you can access any block in same amount of time as any other block. For example, you can access any of the 512 blocks in exactly same amount of time.
So, starting from that statement, I would like to know exactly how the RAM locates, for example, position 1000 (or any 'position X' that the CPU has indicated) in the same time that it can locate position 1.
I imagine it as a matrix but I can't figure out how it can access exactly to position 1000 without having to go through the other positions. How is this position calculated exactly?
In conclusion, I would like to know how to directly access a memory location without going through the other locations.
Thank you very much in advance.
Best Answer
Figure 1. An 8-bit wide random access memory. Image source: ETSU.
Steps:
The diagram alludes to some additional logic such as read/write (to tell whether to put data out on the address lines or to write the contents of the address lines into that memory row) and "chip select" which would be used when more than one memory chip is used.
The position isn't calculated. It is selected. In your example of reading address 1000 you will need at least a 10-bit address bus (which gives 210 = 1024 addresses). 100010 = 11111010002 so the address lines would be set to that binary address, the address decoder will immediately select row 1000 and put the data out on the data bus. Any address can be read at the same speed. (High addresses do not take longer to access or read.)
Figure 2. A 3-to-8 decoder enables the output (Y) selected by the binary address code (X0 to X2). The logic is arranged so that only one output is on for any input combination. Image source: Codestall.
Obviously, a 10-bit addressing scheme would require a correspondingly large decoder.