I have been thinking about this definition a lot today.
As others pointed out, the exact meanings will vary. On top of that, you will probably see more people get this wrong, even on this site, than right. I don't care what wikipedia says!
But in general:
- A flip flop will change it's output state at most once per clock cycle.
- A latch will change its state as many times as the data transitions during its transparency window.
Additionally,
- A flip flop is very safe. Almost fool-proof. For this reason synthesis tools usually use flip flops. But, they are slower than a latch (and use more power).
- Latches are harder to use properly. But, they are faster than flip flops (and smaller). So, custom circuit designers will often "spread the flip flop" across their digital block (a latch on either end with opposite phase) to squeeze some extra picoseconds out of a bad timing arc. This is shown at the bottom of the post.
A flip flop is most typically characterized by a master-slave topology. This is two coupled (there can be logic between), opposite phase latches back to back (sometimes in industry called L1/L2).
This means a flip flop inherently consists of two memory elements: one to hold during the low cycle and one to hold during the high cycle.
A latch is just a single memory element (SR latch, D latch, JK latch). Just because you introduce a clock to gate flow of data into the memory element does not make it a flip flop, in my opinion (although it can make it act like one: i.e. more rising edge triggered). It just makes it transparent for a specific amount of time.
Shown below is a true flip flop create from two SR latches (notice opposite phase clocks).
And another true flip-flop (this is the most common style in VLSI) from two D-latches (transmission gate style). Again notice the opposite phase clocks:
If you pulse the clock to a latch quickly enough, it starts to resemble a flip flop behavior (pulse latch). This is common in high speed datapath design because of the lesser delay from D->Out and Clk->Out, in addition to the better setup time granted (hold time also must increase, small price to pay) by transparency through the duration of the pulse. Does this make it a flip flop? Not really, but it sure looks acts like one!
However, this is much harder to guarantee to work. You must check across all process corners (fast nmos, slow pmos, high wire cap, low wire r; as an example of one) and all voltages (low voltage causes problems) that the pulse from your edge detector remains wide enough to actually open the latch and allow data in.
For your specific question, as to why it is considered a pulse latch instead of a flip flop, it is because you truly only have a single level sensitive bit storage element. Even though the pulse is narrow, it does not form a lock-and-dam system which creates a flip flop.
Here is an article describing a very similar pulse latch to your inquiry. A pertinent quote: "If the pulse clock waveform triggers a latch, the latch is synchronized with the clock similarly to edge-triggered flip-flop because the rising and falling edges of the pulse clock are almost identical in terms of timing."
EDIT
For some clarity I included a graphic of latch based design. There is a L1 latch and L2 latch with logic in between. This is a technique which can reduce delays, since a latch has lesser delay than a flip flop. The flip flop is "spread apart" and logic put in the middle. Now, you save a couple gate delays (compared to a flip flop on either end)!
Best Answer
The JK flop can power up in either state. With perfectly matched gates, the odds would be 50-50 for each state. It is up to the rest of the system to initialize to a known, desired state, or to not care about it. Same goes for a D flop.
It’s the same as having an uninitialized variable in a program. Until the variable is set, any values that depend on it (including itself) are not known.
Hardware simulation of this flop would show up as an ‘X’ state until it has had a 0 or 1 clocked into it. Otherwise, it will stay ‘X’ if both J and K are 0 (hold) or 1 (toggle).
In actual hardware (like software), unknown things could happen depending on how the unknown-state output is used.
A variant of this flop has direct set and clear inputs to force an initial state with separate signals (e.g., reset.) In that case a startup behavior can be defined.
MORE: the logic diagram shown for the JK is crap. This is actually a gated JK latch, and it has a hazard when both J and K inputs are ‘1’ and the clock is high: it becomes a ring oscillator due to the 'race around' issue.
Unfortunately, while the the linked article discusses this, it gives a mealy-mouthed answer about using a very narrow clock pulse to avoid the ‘race around’ issue. This is hugely misleading. Integrated circuit-based JK flops use a pair of latches wired as 2 stages ("master-slave" or "edge-triggered") and don't have the race-around problem.
Another complaint. The logic diagram given for the 74xx73 type JK is not only incomplete (doesn't show set/reset), it's wrong (74xx73 uses the 2-latch "master-slave" design, not gated latch.) I left a note for the page author for them to fix it.
This answer discusses the JK gated-latch problem in detail. SR FlipFlop Question
And here: JK latch, possible Ben Eater error?