Electronic – How to a 4-bit CPU have 40 instructions

The term you want is "dual port RAM", and yes, they exist both as discrete components and as building blocks inside chips such as FPGAs. They are frequently used when it is necessary to pass data from one clock domain to another, and somewhat less frequently as cache storage, which is what you seem to be trying to do.

DDR/QDR (double data rate, and quad data rate, respectively) are something else: they are techniques for improving the bandwidth of the individual connections to a RAM chip.

You can effectively create a memory with two read ports by simply hooking together two normal single-port memories. Connect their write ports to the same source, and use their read ports independently. The contents will always be identical copies.

You will almost certainly need more than one line for the ALU OP. (I doubt that all operations will be ADD or SUB. For example, NOP might be needed.) You mention four, but I see five written there. I think you will be quickly needing instructions to allow multi-precision add and subtract, as well.

You haven't specified how you will arrange your CPU but you will also almost certainly need a line for a latch prior to one of the two inputs to the ALU, if you share a common bus on that side. That line latches a value long enough for you to retrieve a second value and place it onto the bus. You might want a latch for both ALU inputs. If so, that's two lines instead of one.

If you support ADD with carry and SUB with borrow, then you will need two more control lines to allow the Carry-in to be one of four values: 0, 1, \$\overline{C}\$, or \$C\$.

ALU status will need to be captured with another latch -- and its associated control line. If you want to read this ALU status register as data, you'll need a separate latch with a tri-stating control for that. Two more control lines.

You almost certainly will need a latch at the output of the ALU to capture the output after enough time has passed for the combinatorial delay. This latch almost certainly will require a tri-stating input, as well, so that the bus can be shared with your register file, fetched memory values, etc. So that's two lines to this latch.

You say you've achieved some things (like RAM) but haven't said anything about how. So I assume you know the control lines required there. But you will need a program counter (a latch), a way to increment it, and a way to load it, and a way to clear it or set it upon reset. But you will need control lines for these operations.

Your PC register (used for accessing the next instruction) will probably need a prior mux, as well, to get access to registers and/or its adder system. This is distinct from the address bus latch and will require more control lines for the mux.

Outgoing bus values will need a latch to hold the value for the memory bus. That's another one or two control lines (latching and tri-stating output if the external data bus is bi-directional.)

You need a register to hold the current instruction (and possibly the next one, too, depending on how you are managing things.) This register needs to be latched from the incoming data bus at the right time. Another control line for that.

If you have addressing modes (and you have an addi and an add, so you do already), you will need a mux (more lines) and fixed registers to tap into (more lines), in order to support your address latch and separate adder -- oh, that separate adder requires more control lines, too.

You probably will need another mux to reach your external bus address latch, as well. You will at least want to be able to select the output of your addressing adder or alternatively, some register file output. So that's at least one more control line if not more for that mux, too.

Do you have a stack pointer? More control lines. Register file? Still more lines.

You may need special constants -- like 0, -1, 1, 2, and others. And you'll need a mux for that and more control lines.

You will also need a way to gate part of your instruction register, over to the ALU input (latch or on the bus.) Your addi requires this, to access that field. You may need to sign-extend this (gating multiple lanes to the ALU from a single [sign] lane in your instruction) to get +/- constant support. To do this, it means at least a tri-stating control line and probably also an option that widens the lane, too.

If you haven't gotten the point, yet, it should be slowly dawning on you by now (I hope.) You have provided WAY TOO LITTLE information for ANYONE to tell you how many control lines your execution engine must operate and/or respond to.

Personally? I don't think you've done what you say you've done. If you had, you'd have provided exact details about what you had in place and how it is all controlled so that we could have done less work writing and provided a better answer for you. So I actually don't believe you have done all that you say you have.

It's a good idea to try these things out in Logisim. You'll learn a lot and it's a nifty tool. But it also "cheats" in the sense that you can drop down a subtractor separate from an adder without actually learning how these two functions are really done. (A subtractor is just an adder where one of the inputs comes from the \$\overline{Q}\$ output of a preceding latch [via another mux, of course] and where the carry-in is changed. You don't use a separate "unit" for that.) It cheats in many other ways which will stunt your growth, as well. (It ignores glitching problems to name just one of many.)

If you are serious about all this, there are some good books I could recommend to help. Have you been able to find a completed CPU in Logisim? You might start with that.