Electronic – Designing an instruction set for a homebrew computer

cpudesignhomebrew-cpuinstruction-set

I'm going to begin the adventure of building an 8-bit homebrew computer.

Right now, I'm considering the instruction set. SAP-1 seems a bit too sparse, so I'm designing my own.

Some facts:

My primary goal is to learn. I'll be building this on breadboards.
I plan on using 4 bit addresses (so 16 bytes of RAM).
The computer will have a 7-segment display for its output.
I want to be able to easily write simple math programs (addition, subtraction,
multiplication, division). Do I have enough RAM for this?
I plan on using an ALU with zero, sign and carry status bits.
The system will have two registers for computation (A and B).
I'll have additional registers for current instruction and output.
Each machine code instruction will use the 4 highest bits for operation codes and the 4 lowest bits for data.

Here is the instruction set I'm thinking about. Does this make sense? Are any of these redundant/unnecessary? Is anything missing?

0000 | NOP | No-op
0001 | LIA | Immediately load data into A register
0010 | LDA | Load contents of memory address into A register 
0011 | STA | Store contents of A register into memory address
0100 | CAB | Copy contents of A register into B register
0101 | CBA | Copy contents of B register into A register
0110 | ADD | Add contents of memory address to A register
0111 | SUB | Subtract contents of memory address from A register
1000 | INC | Increment contents of A register
1001 | DEC | Decrement contents of A register
1010 | JMP | Jump unconditionally
1011 | JEQ | Jump if ALU zero bit is expressed
1100 | JNG | Jump if ALU sign bit (negative) is expressed
1101 | JCA | Jump if ALU carry bit is expressed
1110 | OUT | Copy A register into output register
1111 | HLT | Halt

Also, please let me know of any good resources for instruction set design, or general homebrew computer design.

I'm currently working through The Elements of Computing Systems and Ben Eater's YouTube videos.

Best Answer

since this is more like feedback: let's have a wiki.

You need some way to store the current (or next) PC. That and a JMP can form a CALL; then you need JUMP (contents of address where you stored it) to RETURN. Stack is a convenient way to handle call/return and a lot of other stuff, but quite a big change to your architecture.
why do you have fused load+arithmetic ops? Wouldn't a "SUBtract value of register B from register A" be significantly more handy? Otherwise you'd first have to STA to do arithmetic.
OUT is a fun operation, but honestly, I'd go the arm route and simply use reserved addresses for that. That is, of course, unless you need all your address space because it's really not that large.
integer-to-seven-segment conversion will be pretty complicated using these instructions, if you can't waste a lot of memory space on a lookup table. So, maybe have an instruction to convert a register value to the appropriate output.
Instead of the two A->B and B->A copy instructions, I'd go with one copy, and a swap instruction.
You have an operation to load 4 bits of an immediate value into an 8 bit registers. How do you set the other bits? Maybe you want a "swap high and low nibble" instruction, or even more versatile, a shift?

Related Solutions

Electronic – Implementing multiplication

At minimum, you need a branching instruction which can determine whether the previous addition generated a carry. Also, performance will be improved enormously if you expand your register set to three or four registers.

Start with one operand in R0 and the other in R1. Start with R2 zero.

Repeat the following sequence eight times (first ADD may be skipped on first pass)

  Add R2,R2
  Add R0,R0
  Bnc Skip
  Add R2,R1
Skip:

Note that if the instruction set includes an add-with-carry instruction, using it for the second instruction would cause this instruction sequence to yield a 16-bit result in R0:R2. Further, if R2 starts non-zero, its value times 256 will be added to the outgoing result.

CISC, microcode execution flow

To understand the behaviour of the CPU you need to know how an instruction is made: there is a fixed part that represent the instruction (let's say that 0001 stands for INC), that is repeated every time you write an INC instruction, and there is a part that depends on the instruction and it's why the CISC processors instructions are not all long the same. The second part contain, in our example, the address of the memory location that we want to increment (0010 0100 1000, assuming that it uses 12 bits to address the memory).

Every instruction set is made in this way. The difference in the instruction set between a CISC and a RISC processor is that the latter uses an instruction set with a fixed instruction width.

The datasheet of a microprocessor can show you exactly how every instruction is made. If you want to see an example of how an instruction is made I advise you to start with old processors datasheet because they are less complex and are easier to understand. Take a look at the Z80 Datasheet, from page 101.

Coming to the question, essentially no. The CISC instruction does not contain the single microcoded instructions, but only a code that identifies the operation we want to do and the necessary data (value to load, address of the memory location...) to execute the instruction. The CPU has a decoder that when read the code knows what to do for that specific instruction and, if it's a microcoded instruction, it knows how to decompose it. As you can see the number of microcoded instructions in which an instruction is divided isn't depending on the lenght of the instruction and it's something "hidden" in the CPU itself, not accessible from the outside. The same goes for the opcode of the "micro" instructions.

This is a simplistic answer, but it tell you essentially how the things works. You can immediately see why the decoder of a CISC processor, particularly if it uses microcode, like the x86 CPUs, is much more complex than its counterpart RISC.

Best Answer

Related Solutions

Electronic – Implementing multiplication

CISC, microcode execution flow

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