# Electronic – How to break multi digit number into separate digits in VHDL

cfixed-pointvhdl

I found the method for c language.But I do not know how to perform this in VHDL.
Let a fixed point number (12 downto -19) like 3456.478396 I need break this number entirely into separate numbers 3456.478396 –> 3, 4, 5, 6, (dot) , 4, 7, 8, 3, 9, 6… into 11 integer type variables.
How to perform this in VHDL?

signal example : sfixed(4 downto -4);
--'example' contains 9.75 then it is storage as "01001.1100".
--simply example ="10011100".
--10011100 --> integer 156


How to get back original 9.75 number from 156 to separate into single digits?

I USED,

library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.float_pkg.ALL;
use ieee_proposed.fixed_pkg.ALL;
use ieee_proposed.fixed_float_types.ALL;


Here's some pseudocode.

Let's take the ones left of the decimal first, max number is \$15_{10}\$ => 2 decimal digits.

signal ex : sfixed(4 downto -4);

temp <= ex(4 downto 0);
L_0 <= temp mod 10;
temp <= temp/10;
L_1 <= temp mod 10;


Example:
ex=\$12_{10}\$=\$1100_{2}\$

temp <= 12
L_0 <= 12 mod 10 = 2
temp <= 12/10    = 1
L_1 <= 1 mod 10  = 1


And then the ones to the right, smallest number => 0.0625 => 4 decimal digits. Same method as before, just multiply by \$625_{10}\$ before you start. Because \$0001_{2}\$ in binary translates to \$.0625_{10}\$ in decimal. So the bit width of temp should be \$ceil(log_2(625×15))=\$ 14 bits because \$15_{10}\$ is \$1111_{2}\$ which is your highest value.

signal ex : sfixed(4 downto -4);

temp <= ex(0 downto -4);
temp <= temp*625

R_3 <= temp mod 10;
temp <= temp/10;
R_2 <= temp mod 10;
temp <= temp/10;
R_1 <= temp mod 10;
temp <= temp/10;
R_0 <= temp mod 10;


Example:
ex=\$0.1875_{10}\$=\$0011_{2}\$

temp <= 3 = 0011
temp <= 3*625 = 11101010011        = 1875

R_3 <= 1875 mod 10                 = 5
temp <= 1875/10                    = 187
R_2 <= 187 mod 10                  = 7
temp <= 187/10                     = 18
R_1 <= 18 mod 10                   = 8
temp <= 18/10                      = 1
R_0 <= 1 mod 10                    = 1


And it should be displayed like this:

\$L_1 L_0 . R_0 R_1 R_2 R_3\$

All the constant division by 10 can be replaced by a multiplication with \$\frac{1}{10}\$. So it's not too inefficient to implement. I'm fairly certain that the modulus operator comes with the standard library.

If you use 6 bits for the right hand side of the decimal point. Then the bit width for temp should be \$ceil(log2(63×15625))\$ = 20 bits. This is probably not the most efficient way, it's a way I came up with just now on my own. It should work without any major problems.

Since this is being done on an FPGA you can parallelize the multiplication, for R3,R2,R1 and R0, multiply their temp with 1, \$\frac{1}{10}\$, \$\frac{1}{100}\$ and \$\frac{1}{1000}\$ so you get the values straight away, instead of serially. And then use the mod 10 on them.

## EDIT

Mishyoshi gave me an idea for how this could be solved in another way. \$L_0\$ and \$L_1\$ are solved like before, but the \$R_{0..3}\$ can be done in another more efficient way.

signal ex : sfixed(4 downto -4);

signal temp : sfixed(4 downto -4);
//We need 4 to the left of the decimal point because then we can capture
//all the single digits

temp <= "0000" & ex(0 downto -4);
temp <= temp*10;

R_0 <= temp(3 downto 0); //Copy the 4 MSB bits
temp <= "0000" & temp(-1 downto -4); //Delete the 4 MSB bits
temp <= temp*10;
R_1 <= temp(3 downto 0);
temp <= "0000" & temp(-1 downto -4);
temp <= temp*10;
R_2 <= temp(3 downto 0);
temp <= "0000" & temp(-1 downto -4);
temp <= temp*10;
R_3 <= temp(3 downto 0);


Example:
ex=\$0.1875_{10}\$=\$0011_{2}\$

signal temp : sfixed(4 downto -4);

temp <= "0000" & "0011"                     = 0000.0011 = 3
temp <= 3*10                           = 30 = 0001.1110
R_0 <= "0001.1110"(3 downto 0)              = 0001 = 1
temp <= "0000" & temp(-1 downto -4)         = 0000.1110
temp <= 14*10                         = 140 = 1000.1100
R_1 <= "1000.1100"(3 downto 0)              = 1000 = 8
temp <= "0000" & "1100"                     = 0000.1100
temp <= 12*10                         = 120 = 0111.1000
R_2 <= "0111.1000"(3 downto 0)              = 0111 = 7
temp <= "0000" & "1000"                     = 0000.1000
temp <= 8*10                           = 80 = 0101.0000
R_3 <= "0101.0000"(3 downto 0)              = 0101 = 5


As you can see it's all about getting the bits to the "ones" place, the 4 bits to the left of the decimal point.

That's way fewer bits needed for this. In this other solution you can, like Mishyoshi said, put them in a pipeline.