Electronic – How to calculate needed pixel clock frequency

The core clock of the CPU isn't received directly from the motherboard. That clock is usually much slower (often by a factor of 10 or more) than the internal frequency of the CPU. Instead, the clock signal from the motherboard is used as the reference frequency for a higher frequency phase locked loop controlled oscillator inside the CPU. The generated clock runs at some multiple of the reference clock, and that multiple can be changed by setting certain registers in the CPU. The actual generation of the clock is done purely in hardware.

To reduce power even further, the CPU also signals to the voltage regulator supplying its core voltage to run at a lower set point. At lower frequencies the CPU can run at a lower voltage without malfunctioning, and because power consumption is proportional to the square of the voltage, even a small reduction in voltage can save a large amount of power.

The voltage and frequency scaling is done by hardware, but the decision to run in a low power mode is made by software (the OS). How the OS determines the optimal mode to run in is a separate, messier, problem, but it likely comes down to mostly what %time has the system been idle lately. Mostly idle, lower the frequency. Mostly busy, raise the frequency. Once the OS decides the frequency to run at, it's just a matter of setting a register.

Reference: "Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor"

To answer such a question a lot more context must be given and assumptions must be made explicit. Just a few issues:

1) The call-method you describe here is typical for ARM/Cortex and some less known architectures. An 8085 uses the more common stack based method.

2) Most architectures have dedicated hardware and data paths for incrementing the PC, so the ALU does not need to be involved, and it can be done in parallel with another operation.

3) An 8085 is an 8-bit architecture with a 16-bit address, hence getting an address from memory involves two memory accesses (with accompanying PC increments).

4) You seem to assume that a memory access takes 2 internal cycles worth of time. IIRC it was 1 for an 8085 (but I might be wrong), and it is often many many more for modern processors.

5) In step 3) you mention an accumulator, you probably mean the ALU result register, which on most register-based architectures is not a programmer-visible register.

6) If storing the result in Rn takes a cycle, it seems reasonable to assume that storing the destination address in the PC also takes a cycle.