Electronic – How to change the clock frequency of a STM32H753ZI

There is more pixels in the video signal than just the x * y * refresh_rate would imply. Back in the bad old days of CRT's, it would take time for the electron beam to move from the end of the current line to beginning of the next. Likewise, it would take time for the beam to move from the bottom of th screen to the top for the next frame. The time it took was built into the video signaling standard, and essentially took the form of pixels that are never seen.

Without knowing the info on these blank pixels (sometimes called "overscan"), you cannot calculate the pixel clock required.

The best way to figure this stuff out is to Google for the approximate video standard you're trying to do, or look at the datasheet for the screen you are trying to drive.

I think that your question is aimed at the program execution speed, and not the clock frequency.

This link has a simple way to explain pipeline. But the picture below (from the site) brings the base information on how the pipeline structure can hurt the execution speed:

From the picture you can see that the pipeline takes advantage of executing two or more tasks simultaneously. The problem is that the period of execution for one cycle is dependent of the longest task in the pipeline. If lots of long tasks enters in the pipeline, the whole chain may suffer the delay. Among these kind of tasks, memory instructions are one of the longest.

If all the memory access are made scattered through the code, the processing time would be higher. If the accesses are grouped, the fast instructions would be executed without the interference of the slower ones.

Other problem that may arise is the junction of pipeline and branch prediction. The prediction tries to guess which is the more probable result from an if instruction and starts to evaluate the guessed path from code even before the result is known. All these instructions are therefore pipelined through the processor. If the guess appears to be wrong, the processor must wait until the pipeline buffer to clear before starting to evaluate the correct path.