There is a need to have a group of signals arrive simultaneously to their respective destinations, given that they start their journey at the same time.
However, due to physical constraints it is not possible to have them routed on the same layer, breaking routing symmetry. In order to calculate their lengths so that flight time is equal, propagation times are needed. I have formulas for microstrip and stripline propagation speeds, but I don't have any for vias. Does anyone have any information about this?
PS:I am aware that nearby ground vias are required for the return path to find a way to switch reference planes.
Best Answer
Via impedance can be approximated by its capacitance and inductance. From pages 257 to 259 of High-Speed Digital Design:
$$ C_{\text{via}} \text{[pF]}=\frac{1.41 \epsilon_r T D_1}{D_2-D_1} $$ D1: diameter of pad surround via [in.]
D2: diameter of clearance hold in ground plane(s) [in.]
T: thickness of PCB [in.]
\$\epsilon_r\$: relative electric permeability of circuit board material
The 10%-90% rise time degradation for a 50\$\Omega\$ transmission line due to this capacitance will be \$ {T_{10-90}}=2.2C_{\text{via}}(Z_0/2)\$.
$$ L_{\text{via}} \text{[nH]}=5.08h\left[ln\left(\frac{4h}{d}\right)+1\right] $$ h: length of via [in.]
d: diameter of via [in.]
Inductive reactance is \$ X_L \text{[}\Omega\text{]}=\pi L_{\text{via}}/T_{10-90} \$. I'll leave making the link between XL and T10-90 degradation to someone who has actually done this.
Total via delay is estimated in the sequel, High-Speed Signal Propagation, on pages 341 to 359, to within an order of magnitude, with the following comment:
$$ t_v=\sqrt{L_VC_V} $$ LV: incremental series inductance
CV: incremental shunt capacitance
The pi model can be applied for a more accurate model. Place half of CV in each cap and the full LV in the inductor. These approximations are only good for frequencies above the onset of the skin effect -- at least 10MHz and preferably 100MHz.