Electronic – Speed of electricity (signal propagation?) through copper for communications delay

Via impedance can be approximated by its capacitance and inductance. From pages 257 to 259 of High-Speed Digital Design:

$$ C_{\text{via}} \text{[pF]}=\frac{1.41 \epsilon_r T D_1}{D_2-D_1} $$ D₁: diameter of pad surround via [in.]
D₂: diameter of clearance hold in ground plane(s) [in.]
T: thickness of PCB [in.]
\$\epsilon_r\$: relative electric permeability of circuit board material

The 10%-90% rise time degradation for a 50\$\Omega\$ transmission line due to this capacitance will be \$ {T_{10-90}}=2.2C_{\text{via}}(Z_0/2)\$.

$$ L_{\text{via}} \text{[nH]}=5.08h\left[ln\left(\frac{4h}{d}\right)+1\right] $$ h: length of via [in.]
d: diameter of via [in.]

Inductive reactance is \$ X_L \text{[}\Omega\text{]}=\pi L_{\text{via}}/T_{10-90} \$. I'll leave making the link between X_L and T_10-90 degradation to someone who has actually done this.

Total via delay is estimated in the sequel, High-Speed Signal Propagation, on pages 341 to 359, to within an order of magnitude, with the following comment:

It makes no sense to define, or to attempt to measure, the inductance of a via without also specifying how the attached traces bring current through it, and how the planes carry the returning signal current.

$$ t_v=\sqrt{L_VC_V} $$ L_V: incremental series inductance
C_V: incremental shunt capacitance

To properly measure [C_V], first measure the static capacitance to the reference planes of a configuration that includes an input trance of length x, the via, and an output trance of length y, where both x and y greatly exceed the clearance-hole diameter. The lengths x and y are measured to the center of the drilled via hole. Then separately measure the static capacitance of a similar trace of length x + y (with no via and no clearance hole). [C_V]... is the difference between your two measurements.

[L_V] is defined similarly, but with each trace shorted to the reference plane at its far end. Arrange your equipment to detect the loop inductance of the path entering trace [x where it is shorted] ..., passing through the short-circuit at the far end of [y]..., and returning through the reference planes to the equipment, [where x is shorted].

The pi model can be applied for a more accurate model. Place half of C_V in each cap and the full L_V in the inductor. These approximations are only good for frequencies above the onset of the skin effect -- at least 10MHz and preferably 100MHz.

If your via is so large compared to the signal risetime that you require anything more than a simple pi-model for the via, then it probably isn't going to work very well for a digital application. Use a smaller via.

If the delay down the copper wire is less than the encoding delay though, surely bits will be being received too quickly at recipient end, faster than they can be decoded into a digital stream which could be buffered?

I think the key point you're missing is that it's entirely possible for more than one bit to be "in flight" on the wire at any given time.

For example, if the wire is 100 m long, and the velocity is 192 x 10⁶ m/s, and the bit rate is 100 Mb/s, then 52 bits of data will actually be "on the wire" at any given time. The receiver, however will only be aware of the 1 bit that is actually arriving at the receiver at that instant.

If the transmitter is sending bits at 100 Mb/s, then the receiver must receive and decode these bits at 100 Mb/s. The length of the wire changes the latency time between these two events, but it has nothing to do with the rate at which the receiver must deal with the incoming data.

Usually the receiver doesn't deal with the incoming bits one at a time, doing calculations at 100,000,000 operations per second. Instead it simply queues the bits up into something like a shift register, and then operates on them at a much lower rate, maybe 12.5 million operations per second, but operating on full bytes with each operation (or even at slower rates, but operating on larger data words).