I am using atmega16, and i need to use ADC feature in my project. As i know that there is a formula to set flag register ADPS2, ADPS1, and ADPS0. Which is used for determine the division factor between the XTAL frequency and the input clock to the ADC. But i don't know, which one the best division factor i need. How to determine? Should i use division factor 2, 4, 8 or?
Electronic – How to choose the best ADC clock
adcatmegaavr
Related Solutions
What is the ADC Clock?
The section that you are seeing is for the clock used for the ADC. This clock is not directly related to the max sampling frequency though. The clock is what is actually being fed to the ADC module which needs to be faster than your sampling so that it can handle some magic for you.
How does the Max clock relate to the max sampling frequency?
What the datasheet is saying is that in order to get 10 bit resolution your clock can not be any faster than 200 KHz. When your clock is at that speed, you will be able to sample your signal at 15,000 samples per second.
If you don't need all 10 bits of resolution then you can provide the ADC with a faster clock and you will get a faster sampling rate, but the datasheet is not clear as to how fast you can go and still get 8 bit resolution.
I would assume that the clock to sample rate ratio is fixed, so 200K/15K = 13.33 which means you can go as low as 50 KHz clock resulting in 3.75 kSPS.
Why a minimum clock to get a 10 bit sample?
The ADC module is doing a sample and hold in which the voltage is essentially held in a capacitor. If you slow the clock down too much, the voltage can start to bleed off of the capacitor before a complete sample is performed. This change in voltage makes it such that you can't get all 10 bits accurately.
So what does this all mean?
According the the Nyquist-Shannon sampling theorem your sampling frequency needs to be at least twice the maximum frequency in your signal. You can learn more about why by looking at this question: Puzzled by Nyquist frequency
So in order to get 10 bits of resolution, the max your signal can be is 7.5 KHz, but if you need to sample a signal faster than that, you can, but the datasheet does not mention how high you can go or how much it hurts your resolution.
It quite clearly says in the data sheet that the ADC clock should not exceed 1MHz. If you break the rules, the behavior is undefined.
It might work, it might not work, it might work only when the moon is full and the temperature is more than 23.7°C or whatever.
Obviously, if your clock is 16MHz, you should not use a lower divider than 16.
Best Answer
As per the datasheet, the ADC must be used with a clock between 50 and 200kHz in order to get accurate results. Too fast and the S+H circuitry won't fully charge. Too slow and the S+H circuitry will discharge before the conversion is complete.
You must choose a prescaler that reduces the ADC clock from the clock control unit to this range. For instance, with a 8MHz system clock a factor of 64 will reduce the clock to 125kHz.