Electronic – How to constrain input delay for a multidimenionsal input vector

asicchip-designconstraintssdcsynthesis

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this module are multidimensional arrays. For example:

input signed [15:0] data_x [3:0][1:0],

data_x is a 3 dimensional vector.

For a vector such as

input signed [15:0] data_y,

to define the input delay, the constraint would be

set_input_delay -clock [get_clock clk] 5000 [get_ports data_y\[*\]]

However, for a multidimensional array input, the following wildcard setup does not appear to match the inputs:

set_input_delay -clock [get_clock clk] 5000 [get_ports data_x\[*\]\[*\]\[*\]]

The following works, but matches other internal signals in the design( such as data_x_d, which is undesirable):

set_input_delay -clock [get_clock clk] 5000 [get_ports data_x*]

Is there a way to specify the name with a wildcard to correctly identify all ports in a multidimensional array?

Best Answer

There is a -regexp option for get_posts. Try:

set_input_delay -clock [get_clock clk] 5000 [get_ports -regexp data_x\[\d+\]\[\d+\]\[\d+\]]

You can get bus ports by their base name. Not sure it it works on multi-dimensional arrays. So this might also work:

set_input_delay -clock [get_clock clk] 5000 [get_ports data_x]

Related Solutions

Electronic – ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock

I'd say that the rule of thumb is: set either input port of the top module, or Q pin of an internal flip-flop as the source of generated clock.

Example Verilog code:

module top (

input clk,
input rst,

...

);

...

always @(posedge clk or negedge rst)
begin
if (rst == 1'b0) 
    div_2_clk = 1'b0;
else
    div_2_clk = ~div_2_clk;           
end

...

endmodule

Example SDC code:

create_clock -name clk -period 5 [get_port clk]
...
create_generated_clock -name slow_clk -source [get_port clk] -divide_by 2 [get_pins div_2_clk_reg/Q]

I did no test the above syntax's. Also note the extension _reg added to the RTL name of the signal - this is the extension added by synthesis tool when it detects that the signal must be represented by a flip-flop. This extension may vary between tools (I don't know for sure).

If you use any RTL wrapper around flip-flops - set the source of the generated clocks to be the internal Q pin of the flip-flop, not the output pin of the wrapper.

If you follow these simple rules you need not worry about any buffers added by the synthesis or P&R tools.

Electronic – ASIC timing constraints via SDC: How to correctly specify a multiplexed clock

Define divide by 1 clocks on the and_* nets and declare them to be physically exclusive. Cadence RTL compiler handles the situation correctly by generating 3 timing paths for registers clocked by cpu_clk (one path each for one clock). Registers directly driven by clk0, clk4 and clk_ext have their own timing arcs.

create_generated_clock -source [get_ports clk0] \
-divide_by 1 -name and_clk0    [get_pins and_cpu_1/Y]

create_generated_clock -source [get_ports clk4] \
-divide_by 1 -name and_clk4    [get_pins and_cpu_2/Y]

create_generated_clock -source [get_ports clk_ext] \
-divide_by 1 -name and_clk_ext [get_pins and_cpu_ext1/Y]

set_clock_groups \
-physically_exclusive \
-group [get_clocks and_clk0] \
-group [get_clocks and_clk4] \
-group [get_clocks and_clk_ext]

Best Answer

Related Solutions

Electronic – ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock

Electronic – ASIC timing constraints via SDC: How to correctly specify a multiplexed clock

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