Electronic – How to specify a minimum clock to output time in output timing constrain

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In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin.

Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some short time after the rising edge of the external clock?

I have looked in the Xilinx Constraints Guide, and it has:

OFFSET = OUT {time_after} AFTER {clock};

But this constraint allows output data to change immediately after the clock, thus with a minimum clock to output time of 0 ps, thereby specifying a duration of {time_after} where the output is undefined.

In compare, for inputs, the constrains is:

OFFSET = IN {time_before} VALID {time_valid} BEFORE {clock};

So here the duration of the defined data can be specified to {time_valid}, but with an independent start time given as {time_before}.

However, it appears that output timing constraints does not have the same flexibility, or I have not found it ☺

Best Answer

The set_output_delay -min SDC syntax does this (Vivado XDC file.) You specify the 'min' value as a negative number as this event happens after the clock.

(What's SDC? Stands for Synopsys Design Constraints, which Xilinx, Altera and others have adopted for specifying timing and other routing / synthesis constraints. With Vivado, SDC replaces the old Xilinx ISE way of doing this. SDC is based on tcl language syntax.)

Generally,

Use an ODDR (Xilinx) clock forwarding scheme to create your external clock. This gives the best control over clock skew, and will give you some hold time by design.
Define this external forwarded clock as a virtual clock using create_generated_clock
constrain your output to the virtual clock using set_output_delay.

More about this here: http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/

And... here: https://forums.xilinx.com/t5/Timing-Analysis/How-to-set-input-delay-and-output-delay-when-source-Synchronous/m-p/940275#M16092

(On Xilinx boards I'm vortex1601. When it comes to timing questions though, Avrum is da man ;-)

Maybe time to migrate to Vivado?

Related Solutions

Electronic – Making combinational component synchronous

I assume that you mean that you have a combinational (not asynchronous) logic which represents critical timing path which limits the frequency, right?

Your Static Timing Analysis (STA) tool have no idea that you allow this component to spend several clock cycles before you expect to get a valid output. Synthesis still thinks that the propagation from the input stage to the output stage should take place in a single clock cycle. It makes its best to optimize this path, but still, the propagation delay is too long.

You have several options:

The best option in such cases is to split the combinational path into few smaller path, and add register for sampling the intermediate results of the reduced paths. This will reduce the propagation delays, but will add latency - you will get the valid output delayed by the number of sampling stages.
If you do not want to mess with this logic (it is too complex, or it is "silicon proven", or any other reason), you can do what you did: add sampling stages before and after the logic, and add additional control logic which knows how many cycles to wait for the valid data (and not allow the inputs to change). However, you must communicate such an unusual intent to all the tools. Information like this was given a general name: "design constraints". Now, I don't know how to specify design constraints for your FPGA (I think it will not take you more than 10 minutes to understand how). What constraint do you need to add? These kind of combinational paths which take more than one cycle are called "multi-cyle-paths" (MCPs). Find it in the documentation of your FPGA\IDE.

NOTE: there is yet another design constraint which may help you - "false path" (FP). When you define some path as FP, no tool will try to derive any timing for this path. This is useful for DFT stuff, clock muxes etc. However, even you may be tempted to use it in this case (FPs are much more simple to define properly than MCPs), don't do it! MCPs constraints must be validated by formal tools, therefore if you define MCP as FP you are masking many potential bugs.

Electronic – ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock

I'd say that the rule of thumb is: set either input port of the top module, or Q pin of an internal flip-flop as the source of generated clock.

Example Verilog code:

module top (

input clk,
input rst,

...

);

...

always @(posedge clk or negedge rst)
begin
if (rst == 1'b0) 
    div_2_clk = 1'b0;
else
    div_2_clk = ~div_2_clk;           
end

...

endmodule

Example SDC code:

create_clock -name clk -period 5 [get_port clk]
...
create_generated_clock -name slow_clk -source [get_port clk] -divide_by 2 [get_pins div_2_clk_reg/Q]

I did no test the above syntax's. Also note the extension _reg added to the RTL name of the signal - this is the extension added by synthesis tool when it detects that the signal must be represented by a flip-flop. This extension may vary between tools (I don't know for sure).

If you use any RTL wrapper around flip-flops - set the source of the generated clocks to be the internal Q pin of the flip-flop, not the output pin of the wrapper.

If you follow these simple rules you need not worry about any buffers added by the synthesis or P&R tools.

Best Answer

Related Solutions

Electronic – Making combinational component synchronous

Electronic – ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock

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