In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin.
Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some short time after the rising edge of the external clock?
I have looked in the Xilinx Constraints Guide, and it has:
OFFSET = OUT {time_after} AFTER {clock};
But this constraint allows output data to change immediately after the clock, thus with a minimum clock to output time of 0 ps, thereby specifying a duration of {time_after} where the output is undefined.
In compare, for inputs, the constrains is:
OFFSET = IN {time_before} VALID {time_valid} BEFORE {clock};
So here the duration of the defined data can be specified to {time_valid}, but with an independent start time given as {time_before}.
However, it appears that output timing constraints does not have the same flexibility, or I have not found it ☺
Best Answer
The set_output_delay -min SDC syntax does this (Vivado XDC file.) You specify the 'min' value as a negative number as this event happens after the clock.
(What's SDC? Stands for Synopsys Design Constraints, which Xilinx, Altera and others have adopted for specifying timing and other routing / synthesis constraints. With Vivado, SDC replaces the old Xilinx ISE way of doing this. SDC is based on tcl language syntax.)
Generally,
More about this here: http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/
And... here: https://forums.xilinx.com/t5/Timing-Analysis/How-to-set-input-delay-and-output-delay-when-source-Synchronous/m-p/940275#M16092
(On Xilinx boards I'm vortex1601. When it comes to timing questions though, Avrum is da man ;-)
Maybe time to migrate to Vivado?