decoderrom;
I used two 9×8 ROMs and used a decoder as enable for both ROMs. Now I have two 8 channel outputs from the two 9×8 ROMs, how am I supposed to make them into a single 8 channel bus? Or is my approach wrong?
Is this question even valid? Here is the actual question our teacher gave us.
"Construct 1K * 8 PROM using two 512*8 PROM. Use enable if needed."
Your approach is correct.
This is probably an error, or oversight, in the textbook: the authors forgot to allow for selecting the final decoder, which is what your 9th decoder does.
There's not a standard formula. First, you have to stack up enough decoders to give you the number of output pins you need. Then, you have to "tree up" enough additional decoders to select the output-layer decoders.
This is a two step problem.
First Step:
Combine your 2k x 8 ROMs into a 2k X 32 ROM (requires 4 x 2k x 8 ROM ICs per 2k x 32 unit)). The address inputs will be common and need to be connected in parallel. The data outputs are kept separate to for the 32 lines required. Don't forget there are also control lines, usually a chip enable and a read line (usually active LOW) but check the specs.
Second Step
This involves combining four "2k x 32 bit" ROM units. The input ADDRESS LINES (A0 - A10) are connected together in parallel. The OUTPUT DATA lines are also connected together in parallel. This just leaves the problem of the CONTROL LINES. The READ line is simply commoned as you want the ROM to output the data with a single 'read' signal. The CHIP ENABLE lines are used as an extra ADDRESS signal to ensure that only ONE 2k x 32 bit block is addressed at any given time. We have input addresses A11 and A12 to give the full 8K address for the ROM. We need to add a 2 to 4 line decoder to convert these address lines to CHIP ENABLE selections.
Best Answer
Yes, it's a valid question, and you've just about got the whole answer already.
Let's call the PROMs U0 and U1. Assuming the decoder Enable selects U0 when A10=0 and U1 when A10=1.
The A0-A9 address bus drives both PROM address inputs. The decoder ensures that only one PROM is enabled, depending on the A10 address input. So D0-D8 will be driven by the U0 PROM when A10 is 0, and D0-D8 will be driven by the U1 PROM when A10 is 1.
Since the decoder never enables both U1 and U2 at the same time, it's legal to connect the U0 D0-D8 outputs and the U1 D0-D8 outputs to the same data bus. (This would not be OK if both outputs could be enabled to drive at the same time, because each signal can only have one source.)
This is very commonly done in FPGA where there are small block memory units available, that can be stitched together into larger memory banks as needed.