Electronic – How to define a clock in Quartus II

fpgaintel-fpgaquartus-iivhdl

I have this piece of code here: 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity first is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
result : out STD_LOGIC_VECTOR(3 downto 0);
clk : in STD_LOGIC
);
end first;

architecture behavioral of first is
begin
process(clk)
begin
result <= a + b;
end process;
end behavioral;

In Quartus II, how can I tell the software that I want 'clk' to be a clock so that I can find out the maximum frequency (Fmax) at which this design can run? Whenever I compile my design I get the warning 'No clocks defined in design'.

Best Answer

The problem is that you actually have no clock, or to be more precise, no clock is used. Check your process:

process(clk)
begin
    result <= a + b;
end process;

This process doesn't use the clock. You probably wanted to do this:

process(clk)
begin
    if rising_edge(clk) then
        result <= a + b;
    end if;
end process;

This code uses the clock and Quartus should report it.

Update

If this is your top-level, it won't have a fmax value for the clock because it has no register-to-register path. Your input signals a and b are not registered, thus the absence of register-to-register path. You can easily solve this:

process(clk)
begin
    if rising_edge(clk) then
        a_r <= a;
        b_r <= b;
        result <= a_r + b_r;
    end if;
end process;
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