Electronic – How to define VHDL entity with two architectures

digital-logicvhdlxilinx

Currently I have one 'adder' entity with two architectures: (1) RippleCarryAdder (2) CarryLookAheadAdder.

I put all the definitions in one single VHDL file as below:

entity adder is
generic (N: integer := 16);
  Port ( Cin : in  STD_LOGIC;
      x : in  std_logic_vector (N - 1 downto 0);
      y : in  std_logic_vector (N - 1 downto 0);
      s : out  std_logic_vector (N - 1 downto 0);
      Cout : out  STD_LOGIC);
end adder;

architecture RippleCarryAdder of adder is
begin
  ...
end RippleCarryAdder;

architecture CarryLookAheadAdder of adder is
begin
  ...
end CarryLookAheadAdder

Using ISE 14.7 Xilinx I can see that the tool has difficulty to properly distinguish two architectures associated to 'adder' entity. It only recognizes the last architecture specified in the file (in this case 'CarryLookAheadAdder').

I guess there is something with file domain, or maybe some rules that govern the architecture declaration which I am not aware of. Strange that the VHDL documentation has not talked about multiple architecture and file structure. Should I use two files, and copy entity declaration in both of them? Can you point to a page that properly discusses multiple architectures format supported by Xilinx ISE? (for example configuration keyword is not supported and I have to resort to another format to bound architectures.)

Best Answer

To use multiple architectures in a single entity, the structure you're looking for (I believe) is configurations. I could never make heads or tails of configurations, and the usage is arcane as best I can tell. Best of luck if you try it.
The half-assed way of doing it would be to use an if generate statement with a generic parameter selecting which instantiation to use. This requires having seperate entities for each architecture, and third entity to act as a wrapper around the generate statement.
The really lazy way would be to just directly instantiate your HalfAdder and RippleCarryAdder as seperate modules, and ignore the headache altogether.

I've never attempted any of this, and I haven't used ISE in years. I don't know if it does support funky configurations, and it honestly wouldn't surprise me if didn't. Like everyone else was saying, I'd suggest upgrading to Vivado

Related Solutions

Electronic – VHDL: Component vs Entity

Here's an analogy which helps some people (especially those from a physical electronics background):

A component tells the compiler "there's going to be something with these sorts of pins on it called this at some point, but don't worry for now". It sort of defines a "socket". You can go on to describe what "wires up" to that "socket" etc.

An entity is something specific with a name and a set of pins, which the compiler can then "plug in" to that "socket" (and hence be connected to the "wires").

Note that you don't need a component you can do "direct instantiation" which means the compiler already knows about an entity so the "socket" doesn't need to be defined separately. In fact, that would be my recommended approach, as otherwise the component is an extra level to be kept in sync.

You need to use components if you are mixing Verilog and VHDL and need to use a Verilog block within the VHDL. Then the component is the socket and not until much later on can the compiler/elaborator plug the Verilog into the socket.

Electronic – Wrong outputs in VHDL entity

The first thing I see, which isn't likely causing your problem, is a lack of any kind of reset. ModelSim does not automatically declare all signals to be '0', and trying to say s <= not s when s is not 1 or 0 is not going to give you what you want. I see you declaring them all '0' at the top but a proper circuit would have a reset input that you briefly drive at the start of your simulation.

Your basic counter process looks wrong; basically when the count reaches ten you're outputting a '1' and for the other 9/10ths of the time you're outputting a '0' (for the 100k example, the 1Hz example would be a 1us pulse high and a 999us low time. I think what you want is something like this:

gen_clk100: process(clk, rst)
begin
    if rising_edge(clk) then
        if count = 10 then
            clk100 <= not clk100;
            count <= 0;
        else
            count <= count + 1;
        end if;
    end if;

    if rst = '1' then
        clk100 <= '0';
        count <= 0;
    end if;
end process;

Note several things:

I'm not incrementing all the time. I increment if the count is not at its max, and increment otherwise.
I'm toggling the output clock when the maximum count is reached
I've included an asynchronous reset (with synchronous clear) -- this ensures that your signals initialize correctly and have no metastability problems when reset is released.

You also mention that the other sections are the same. I think you're having a problem with multiple drivers like Yann mentioned. Check and double-check your code to make sure you are not assigning the output in two different processes, because that is exactly what the simulation is saying you're doing. Better to either make a generic counter module or...

Why so many counters? All your frequency dividers can be handled with a single count and then "peeling off" the conditions to do the divisions you're interested in. You could also have a single counter and use the mod (modulus) operator to handle each divider case.

Finally, I'd also use real or integer types for the count instead of std_logic_vectors but that's just me.

Best Answer

Related Solutions

Electronic – VHDL: Component vs Entity

Electronic – Wrong outputs in VHDL entity

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