Electronic – how to implement a low pin count stereo display (FPGA)

fpgaverilog

I need to design a TX/RX pair which functions like a HDMI 1.4 3D, for a proprietary HUD. The source signals are 2 distinct TFT output in RGB, and the sinks are also two separate OLEDs, and a stereo audio also need to be transferred in the same cable, but is on a lower priority.

The purpose is to reduce pin count of the cable connector.

LVDS signals on Xilinx spartan 6 could be transferred in meaning as GTP(PCIe) or SelectIO(TM) through IOB. The bandwidth estimation is about 600Mb/s in XVGA(single line).

Should i build a SerDes to bundle DVI(HDMI)signal in PCIe, or build something from scratch.

Thanks for your reading and your comment is valuable.

Best Answer

Like Martin said, an Aurora implementation is eminently doable. It can also be done with a single differential pair vs 4 pairs for a dvi implementation. The clocking requirements for gtp transceivers can be pretty strict and the synchronization of the video can pose some challenges so make sure you understand ug386 and any other applicable Xilinx user guides.

A hdmi transmitter->receiver pair will work for you and might be simpler than a transceiver based solution. Hdmi is just dvi with some extras that you do not Ned added on, generally hdmi transmitters and receivers are backward compatible with dvi. Both are based on TMDS serial links, 3 data and 1 clock (4 differential pairs). When you control both ends of the link as long as you meet the basic requirements of the dvi standards for the (de,hsync,vsync) timing signals you can send any resolution you need. It does not need to be a standard video resolution.

Another potential solution is to use cameralink using the iserdes and oserdes blocks in spartan 6.

With any solution you will have to make sure the cable and board designs have have the needed signal integrity characteristics.