How to Truncate the Least Significant Bits in a Verilog Assignment

verilog

I have a register of around 120bits, where data is shifted in lsb first, at some point I want to assign it to smaller registers but instead of truncating the most significant bits, I'd like to truncate the least significant bits. In essence I want to keep the n most significant bits of a register.

The current way I'm doing it is for each register assign from MSB index of big register for a width of register width like:

rSmall1 <= rBig[BIG_REG_MSB_INDEX -: RSMALL1_WIDTH];
rSmall2 <= rBig[BIG_REG_MSB_INDEX -: RSMALL2_WIDTH];
[...]
rSmalln <= rBig[BIG_REG_MSB_INDEX -: RSMALLn_WIDTH];

While it works it clutters up pretty fast so, Is there a simpler way to do this same operation for any width of rSmalln?

Best Answer

There is no easier way to do this in Verilog. A logical shift right requires similar width parameters.

This would be easier using SystemVerilog's streaming operator which left justifies assignments.

bit [BIG_REG_MSB_INDEX:0] filler;

{{>>{rSmall1,Filler}} <= rBig;
{{>>{rSmall2,Filler}} <= rBig;

Related Solutions

Electronic – How to truncate an expression bit width in Verilog

You can use another variable, though this is not particularly elegant.

wire[31:0] y;

assign y = func(A) ^ func(B);
assign x = y[15:0];

A better approach would be to use a function.

function [15:0] trunc_32_to_16(input [31:0] val32);
  trunc_32_to_16 = val32[15:0];
endfunction

assign x = trunc_32_to_16(func(A) ^ func(B));

Electronic – How is the assignment squence in Verilog

always @(negedge GCLK)
   foo<= bar; // foo is equal to bar in this cycle or next?

For simple cases where there is nothing going on elsewhere in your code to cause bar to change simultaneously with GCLK, this block says, when a negative-going edge is seen on GCLK, "immediately" change the value of foo to whatever bar is at that instant.

"Immediately" means something like one simulation tick after the negative edge arrived.

This means that any other tranisitions that happen on the same negative edge of GCLK and depend on the value of foo will see the old value of foo. But foo will have the new value starting right away until the next negative edge of GCLK.

Edit in reply to comments,

If "any other transitions" see the old value of foo, can we assume that foo is "is available in next clock"?

In the simulator, yes. In real life you need to check propagation delays and setup and hold times to be sure.

what if we put always code with begin...end ? All of them will be immediate ? as: always@(negedge GCLK) begin .. foo<=bar; x<= foo+1; end In this example x will be bar+1 in the same cycle as foo assignment ?

No, as mentioned before, any other tranisitions that happen on the same negative edge of GCLK and depend on the value of foo will see the old value of foo.

If you want the other behavior you can use blocking assignment:

...
foo = bar; 
x = foo+1; 
...

Modern synthesis tools should be able to compile this correctly but old tools might not be able to. What the modern tool will do is simply translate this to

foo <= bar;
x <= bar+1;

and compile that. Since I learned Verilog before this behavior was reliable I find it less familiar to read the code with blocking assignments.

Can we use blocking assignments for immediate and non-blocking for "delayed" assignments?

I'm not quite clear what you mean by this. What a blocking assignment does (in the simulator) is prevent the next statement from executing until after it is complete. Both types of assignment are immediate, but the blocking assingment causes the next statement to be delayed.

If so, it can be a very useful approach for making small delays in the code

For small delays in simulation you can just use delay events

always @(event) begin
   foo <= x;
   #5 
   bar <= foo;
end

For small delays in synthesized code, you'd better be sure the hardware can actually do what you're asking for.

Best Answer

Related Solutions

Electronic – How to truncate an expression bit width in Verilog

Electronic – How is the assignment squence in Verilog

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