Electronic – How to use global clock in VHDL

programmable-logicquartus

I'm teaching myself CPLD programming using a development board with an Altera MAX II EPM240.

After learning how to make a 4-bit digital counter in VHDL using clock/reset inputs, I'd like to use the onboard 50MHz oscillator wired to pin 62. I understand it is fed to the Global Clock Network, but how do I wire it to an input of my VHDL design? (in my case CLOCK)

entity Foo is
    port(
    CLOCK: in std_logic;
    LED_0: out std_logic
    );
end Foo;

architecture rtl of Foo is
begin   
    LED_0 <= CLOCK;
end rtl;

I know I can assign I/O pins to my design with the Pin Planner tool in Quartus II 13.1. I tried assigning pin 62 to the CLOCK signal, but I see no visible output to LED_0 (one of the onboard LEDs). I'd expect to be half-lit, but it's always on. I suppose it's because I'm now trying to use pin 62 as a regular I/O, which is not what I want.

The datasheet mentions LAB column clocks, and signals like labclk1 or labclkena1, but I have no idea how to reference them. As far as I can tell, the signal names I define in my VHDL design aren't related to any internal signals of the chip it will run on.

How do I tell (either in VHDL or with the Quartus tools) that I want one of my input signals to be connected to one of the Global Clock Network clocks?

Best Answer

I would try actually using it as a clock; i.e. clock a register or a counter from it. (Then use the last bit of the counter to drive the LED). That gives the tools a chance to identify it as a clock and route it appropriately. They are pretty good at that.

Related Solutions

Why is ISE / XLS is mapping a signal to the global clock GCK0

Without knowing more about your design, we can only guess.

Most likely, you connected the CLK (or XXX) signal to the clock pins of one or more flip-flops.

That is probably enough for the tool to recognize it as a clock and route it on the global clock routing.

In a comment, you add:

it's hard to imagine how a designer could make the leap that any CLK pin should be connected to a real clock.

There's no requirement that the signals on the GCK nets be "real" clocks, meaning periodic signals with 50% duty cycle. What distinguishes GCK nets is that they have high fan-out, across the whole chip (not just one region), and they have dedicated routing resources (switches) that can connect them to the clock pins of the flip-flops.

So when you route any signal to the clock pin of a flip-flop, the synthesis tool will see that as a candidate for a GCK net. If you have fewer nets connected to flip-flop clock pins than there are available GCK nets, it will probably route all of them via GCK resources. If you have more nets connected to clock pins than there are GCK nets, it will probably prioritize the ones with the highest fan-out.

The tool might also prefer to route clocks on GCK nets, in order to keep other routing available for logic signals that can't use those resources.

This can actually be a problem in some designs. GCK nets have the best propagation delays for nets with very high fan-out. But if your signal actually has low fan-out it might actually be faster to route it on regular logic routing or a regional clock net (I haven't gone back and looked exactly what kind of routing is available in Coolrunner-II). Nonetheless the tool might choose to route clock signals on dedicated clock nets. A synthesis or place & route directive may be needed to get the best performance in these situations.

Of course, the synthesis tool is extremely complicated and we can often only guess what's going on under the hood. You may be able to concoct a situation where the tool fails to recognize a clock and doesn't use the GCK nets. For example, if you route a signal to both clock pins and combinatorial logic, that might change the tool's understanding of its function.

Coolrunner2 GSR Global Set/Reset

As Nick Johnson says, the toolchain should automatically use the Global Set/Reset nets if it thinks it is optimal to do so. All you have to do is use a single signal as an asynchronous reset in all of your logic.

However, if you for any reason do want or need to use the GSR nets directly it is possible:

On the CoolRunner-II devices the GSR pin is a specific input pin. Look at the specific part datasheet (available from the Xilinx website) to find the pin. You must still declare a top level signal which will represent the connection to the GSR pin.

You can then instanciate the Xilinx primitive BUFGSR module to explicitly use the input through the special GSR input buffer. Documentation of this is in Xilinx UG606 - CPLD Libraries Guide, page 82.

Here is a minimal example using the GSR directly:

library ieee;
use ieee.std_logic_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;  --BUFGSR and other primitives are defined in the Xilinx VComponents library

entity gsr_test is
    port ( CLK : in std_logic;
           Reset : in std_logic;
           Inp : in std_logic_vector (3 downto 0);
           Outp : out std_logic_vector (3 downto 0)
          );
end gsr_test;

architecture Behavioral of gsr_test is

signal s_gsr : std_logic;  --signal which will represent GSR internally

begin

--instansiate a BUFGSR to get direct access to the GSR net
i_bufgsr : BUFGSR
    port map ( I => Reset,  --signal/port which supplies the GSR net (this will need to be connected to the GSR pin on the device
               O => s_gsr  --bring the internal signal out
              );

pass_through : process (CLK, s_gsr)
begin
    if (s_gsr = '1') then
        Outp <= "1010";  --when GSR is high set to specific value
    elsif rising_edge(CLK) then
        Outp <= Inp;  --otherwise pass out the value of Inp
    end if;     
end process pass_through;   

end Behavioral;

This generates simple logic with flip-flops for each element of the Outp signal with either their PRE or CLR inputs connected to the GSR net.

Here is a technology schematic of the resulting logic: Technology schematic of minimal solution

Best Answer

Related Solutions

Why is ISE / XLS is mapping a signal to the global clock GCK0

Coolrunner2 GSR Global Set/Reset

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