In your previous question you ran afoul of using the wrong terminology. What you are describing as a chip, technically is NOT an ASIC but would fall under the domain of a "full custom IC", this is the domain of analog circuits, sensors, ADC's, DAC's etc.
Some of the same tools and techniques are used in sub-blocks in Full Custom designs, but what is lacking in an ASIC flow are standard blocks for inductors, antennae, RF modulators etc.
- and again, this is not universal as some companies have some of these cells available.
So the answer is not so black and white. The other issue is that there are very few chip designers on this exchange so you get "sort of right" answers. the details are what matters however.
Lets' talk foundry facing costs:
1st there is MOSIS
- which is a shuttle for many foundries across universities and industry.
2nd there are shuttle runs at a given foundry
The costs given in the other post for shuttle runs are approximately right, you get a limited amount of die at low cost, this applies to MOSIS and shuttles in general. It is NOT a manufacturing solution as you cannot run that maskset again. More for proof of principle. Yields can be terrible because you cannot control what other people are putting down and that can affect your design.
3rd there is MLM at given foundry
- this is a Multi Layer Mask - which means that on a given mask there are reticles for multiple layers. - meant for small scale manufacturing and is meant to reduce the cost of NRE (MASK costs). For 180nm on 200 mm wafers (the reason I choose this is below), this will come in at around $10K, and around ~$2000 per wafer for a minimum of 12 wafers, you'd typically run 20 or more wafers with splits. So maybe $25K.
I have done designs (5 so far)for customers where they ran a MLM mask set once, and then the 25 wafer lot stands them in good stead to support production for the next 5 years. Foundry was cool with that.
4th there is full mask set - for volume production. NRE for fracture and masks will run you ~ $40K - $60K. Wafers will run you $1000 - $1100 for low volume lot start. So with NRE and the lot pricing the first lots out will cost you around $100K. Costs can go as low as $600.
All the above assumes that you have the GDSII databases ready to run.
To get the layout and design done will cost you extra, mainly in labor costs. And tool costs.
- as a bare minimum you'd need 1) a schematic tool, 2) Spice tool (you get the spice decks from the foundry) 3) layout tool, 4) LVS, DRC verification tool.
I'd recommend that you use industry standard LVS/DRC tools from Cadence or Mentor. THese are expensive but there are many contractors who can do chip sign off for you using those tools for $3K -> $10K depending upon complexity. Which beats renting the tool at $300K per year and having to learn how to use it. But some grad student might be able to sneak in a run for you.
If you have a lot of digital you are now talking about these sub-blocks being more in the classical ASIC flow with Verilog/VHDL and then a Synthesis (using a library from the foundry) and then Place & Route (P&R) software to get the layout. The synthesis and P&R tools are even more expensive per year.
Why did I choose 180 nm - 200 mm? Well there are a number of foundries that are running these processes. RF/ID doesn't run that fast - but 180 nm can go as fast as 1.5 GHz, which an handles an RFID chip easily. And since these foundries are fully amortized they are relatively inexpensive. I know of 4 -5 different foundries that will do one off runs and low volume.
If you decide you want sub 65 nm and 300 mm wafers then all these costs go out the window.
It really comes down to experience. IF you haven't done it before then the learning curve is daunting and the chance of getting a chip running the first time is very low.
In experienced hands the design side could take $20K up to $2 Million, depending upon the design, it's complexity and the team's experience.
For small chips you can estimate # of chips per wafer by dividing area of wafer by area of die. Use 180 mm (not 200 mm as there is a 10 mm boundary around the outside of the wafer) for wafer diameter. also increase you die size by 100 u on width and also on height for the scribe lanes. So if you have a 1mm by 1mm die this will get you Pi*90^2/1.1^2 ~= 21,000 gross die.
Die size can be estimated with by searching on line for transistor density figures that are published.
Best Answer
Too give the best chance of a device working as expected in an asic cell library we used to work in a system of increasing abstraction.
The spice models for the technology would be written based on mos transistor theory and verified against a test chip which contained a few devices. The Transistor theory always seemed to be fairly accurate but we were not dealing with sub micron technology with a bunch of secondary effects at the time.
This spice model would be used to develop the rest of the cells in the library. These cells would be put on a test chip. This would be manufactured out at the "corners" of the technology. This involves deliberately introducing manufacturing variation (doping,geometry etc) to give fastest and slowest cases. The test chip would be evaluated to produce the digital simulator models which would be used for individual device design.
I don't go back to the days of rubylith but I can remember doing manual checks of cell connectivity on coloured transparent prints (one per layer) before computer CVS (connectivity verification by computer). Took a few days for a 3k gate asic.
In the earlier days when the whole thing was done by cutting rubylith getting and measuring the right dimensions was critical, but the devices were very simple. In the early days of CAD the cells were put down as cells in cookie cutter form and by that stage we were able to assume that the computer generated geometries within a cell and for connectivity were correct.