Electronic – How to estimate chip area from verilog design

integrated-circuitverilog

I can synthesis the verilog design in Xilinx Vivado (Webpack) and get the LUT/FF usage from the synthesis report.
However, I'd like to estimate the chip area (in mm2) under certain ASIC (not FPGA) spec (for example in 22nm process).

Some articles claim that they got the area with Synopsys Design Compiler, which I cannot access to.

So are there any tools that I can use to estimate chip area from (synthesized) verilog design?

Update:

After some research, i tried qflow 1.1 with osu035 standard cell library for the following verilog code:

module test(
    input a,
    input b,
    output c
);

assign c = a + b;

endmodule

After qflow synthesize place, synth.log gives following area data:

----------------------------
Total stdcells     :4
Total cell width   :2.08e+03
Total cell height  :8.00e+03
Total cell area    :4.16e+06
Total core area    :4.16e+06
Average cell height:2.00e+03

But I have no idea which is the unit of the result.
The osu035_stdcells.lef contains following lines:

UNITS
  DATABASE MICRONS 1000 ;
END UNITS

Therefore, my best guess is the chip area is 4.16e+06/1000/1000=4.16 micron^2 or 4.16e-6 mm2. It that right?

Best Answer

The only way to get a really good estimate is to actually run the design through the proper ASIC flow for the process in question. Yes, this requires extremely expensive software, component libraries, proprietary fab data, etc, etc.

You might be able to get a ballpark estimate by synthesizing to gates (not LUTs) with some other toolchain (perhaps even an open source one) and then multiplying gate count by the cell size for the process you're interested in. Note, however, that certain optimizations to utilize FPGA LUTs and other features won't necessarily work well/at all in an ASIC. This also won't work for designs that use FPGA block RAM or large ROM lookup tables without doing some extra work to exclude the RAMs/ROMs from synthesis as gates and then work out the area of each RAM/ROM individually and add it all up.

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