Electronic – Is this design legal in verilog

verilog

I am trying to simulate a mips-like processor using verilog. Since I am new to verilog, so I do not know if the design is correct or not. Here is the sketch of my design.

Each storage element (Register file,datamemory,AlusourceA,AluSourceB..etc) is defined in a separate module alongwith the functionality to write on that storage element. The control signals and necessary data,address are provided by hierarchical reference to other modules.

Here is an example of a module which explains my design clearly.

     /* top is the main module in this example, all
       modules are instantiated in top module. One or more registers are 
       instantiated in each module which are updated based on the contents 
       of registers in other modules using hierarchical reference*/



     module dat1dat2(input clk,output alusrca,output alusrcb);
     reg [7:0] data1,data2; /*Registers which will be cross referenced in 
                             Alu module*/
     always @(posedge clk)
     begin

     if (top.control_unit_uut.en_dat1dat2 and !alusrcb )
     /*hierarchical reference to a register in a module instantiated in top 
     module*/ 
     begin
     data1<=top.regfile_uut.regfile[top.IR_uut.IR[12:10]];
     data2<=top.IR_uut.IR[6:0];
     end

     elseif (top.control_unit_uut.en_dat1dat2 and alusrcb)


     begin
     data1<=top.regfile_uut.regfile[top.IR_uut.IR[12:10]];
     data2<=top.regfile_uut.regfile[top.IR_uut.IR[9:7]];
     end 
     else
     begin
     data1<=8'hzz;
     data2<=8'hzz;
     end
     end
     assign alusrca=data1;
     assign alusrcb=data2;
     endmodule

Is this design legal in verilog given that I don't have to synthesize it, I just need to simulate it? If the answer is no, what is the simplest design I can use which is not necessarily synthesizable?

PS: If something is still unclear about my question, I can explain it in comments or update my question.

Best Answer

Yes, direct assertions are legal in Verilog. However, this is a very bad design practice to design main RTL code using direct assertions.

The direct assertions in Verilog are usually used in verification environment, in test benches, to "hot wire" some initial states and change timing parameters, mostly in order to accelerate verification process. In this way the verification environment doesn't interfere with main RTL during debug.

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